r254251 - ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply

Sun Nov 29 12:40:07 PST 2015

Hi,

This is entirely the wrong way to do these tests. They shouldn't depend on
assembly output or optimization. Please split them onto frontend IR tests
and backend assembly tests.

Thanks!

On Sun, Nov 29, 2015, 2:56 AM Alexandros Lamprineas via cfe-commits <
cfe-commits at lists.llvm.org> wrote:

> Author: alelab01
> Date: Sun Nov 29 04:53:28 2015
> New Revision: 254251
>
> URL: http://llvm.org/viewvc/llvm-project?rev=254251&view=rev
> Log:
> ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply
> Add/Subtract.
>
> Add missing tests that accidentally were not committed in rL254250.
>
> Differential Revision: http://reviews.llvm.org/D14982
>
> Added:
>     cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c
>     cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c
>
> Added: cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c
> URL:
> http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c?rev=254251&view=auto
>
> ==============================================================================
> --- cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c (added)
> +++ cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c Sun Nov 29
> 04:53:28 2015
> @@ -0,0 +1,128 @@
> +// REQUIRES: aarch64-registered-target
> +
> +// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
> +// RUN:  -target-feature +v8.1a -O3 -S -o - %s \
> +// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
> +
> + #include <arm_neon.h>
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlah_laneq_s16
> +int16x4_t test_vqrdmlah_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) {
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h,
> {{v[0-9]+}}.h[7]
> +  return vqrdmlah_laneq_s16(a, b, v, 7);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlah_laneq_s32
> +int32x2_t test_vqrdmlah_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) {
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s,
> {{v[0-9]+}}.s[3]
> +  return vqrdmlah_laneq_s32(a, b, v, 3);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlahq_laneq_s16
> +int16x8_t test_vqrdmlahq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v)
> {
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h,
> {{v[0-9]+}}.h[7]
> +  return vqrdmlahq_laneq_s16(a, b, v, 7);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlahq_laneq_s32
> +int32x4_t test_vqrdmlahq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v)
> {
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s,
> {{v[0-9]+}}.s[3]
> +  return vqrdmlahq_laneq_s32(a, b, v, 3);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlahh_s16
> +int16_t test_vqrdmlahh_s16(int16_t a, int16_t b, int16_t c) {
> +// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}},
> {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}
> +  return vqrdmlahh_s16(a, b, c);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlahs_s32
> +int32_t test_vqrdmlahs_s32(int32_t a, int32_t b, int32_t c) {
> +// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
> +  return vqrdmlahs_s32(a, b, c);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlahh_lane_s16
> +int16_t test_vqrdmlahh_lane_s16(int16_t a, int16_t b, int16x4_t c) {
> +// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}},
> {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[3]
> +  return vqrdmlahh_lane_s16(a, b, c, 3);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlahs_lane_s32
> +int32_t test_vqrdmlahs_lane_s32(int32_t a, int32_t b, int32x2_t c) {
> +// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
> +  return vqrdmlahs_lane_s32(a, b, c, 1);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlahh_laneq_s16
> +int16_t test_vqrdmlahh_laneq_s16(int16_t a, int16_t b, int16x8_t c) {
> +// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}},
> {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[7]
> +  return vqrdmlahh_laneq_s16(a, b, c, 7);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlahs_laneq_s32
> +int32_t test_vqrdmlahs_laneq_s32(int32_t a, int32_t b, int32x4_t c) {
> +// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
> +  return vqrdmlahs_laneq_s32(a, b, c, 3);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlsh_laneq_s16
> +int16x4_t test_vqrdmlsh_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) {
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h,
> {{v[0-9]+}}.h[7]
> +  return vqrdmlsh_laneq_s16(a, b, v, 7);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlsh_laneq_s32
> +int32x2_t test_vqrdmlsh_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) {
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s,
> {{v[0-9]+}}.s[3]
> +  return vqrdmlsh_laneq_s32(a, b, v, 3);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlshq_laneq_s16
> +int16x8_t test_vqrdmlshq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v)
> {
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h,
> {{v[0-9]+}}.h[7]
> +  return vqrdmlshq_laneq_s16(a, b, v, 7);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlshq_laneq_s32
> +int32x4_t test_vqrdmlshq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v)
> {
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s,
> {{v[0-9]+}}.s[3]
> +  return vqrdmlshq_laneq_s32(a, b, v, 3);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlshh_s16
> +int16_t test_vqrdmlshh_s16(int16_t a, int16_t b, int16_t c) {
> +// CHECK-AARCH64: sqrdmlsh {{h[0-9]+|v[0-9]+.4h}},
> {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}
> +  return vqrdmlshh_s16(a, b, c);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlshs_s32
> +int32_t test_vqrdmlshs_s32(int32_t a, int32_t b, int32_t c) {
> +// CHECK-AARCH64: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
> +  return vqrdmlshs_s32(a, b, c);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlshh_lane_s16
> +int16_t test_vqrdmlshh_lane_s16(int16_t a, int16_t b, int16x4_t c) {
> +// CHECK-AARCH64: sqrdmlsh {{h[0-9]+|v[0-9]+.4h}},
> {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[3]
> +  return vqrdmlshh_lane_s16(a, b, c, 3);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlshs_lane_s32
> +int32_t test_vqrdmlshs_lane_s32(int32_t a, int32_t b, int32x2_t c) {
> +// CHECK-AARCH64: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
> +  return vqrdmlshs_lane_s32(a, b, c, 1);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlshh_laneq_s16
> +int16_t test_vqrdmlshh_laneq_s16(int16_t a, int16_t b, int16x8_t c) {
> +// CHECK-AARCH64: sqrdmlsh {{h[0-9]+|v[0-9]+.4h}},
> {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[7]
> +  return vqrdmlshh_laneq_s16(a, b, c, 7);
> +}
> +
> +// CHECK-AARCH64-LABEL: test_vqrdmlshs_laneq_s32
> +int32_t test_vqrdmlshs_laneq_s32(int32_t a, int32_t b, int32x4_t c) {
> +// CHECK-AARCH64: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
> +  return vqrdmlshs_laneq_s32(a, b, c, 3);
> +}
> +
>
> Added: cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c
> URL:
> http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c?rev=254251&view=auto
>
> ==============================================================================
> --- cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c (added)
> +++ cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c Sun Nov 29 04:53:28
> 2015
> @@ -0,0 +1,121 @@
> +// RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \
> +// RUN:  -O3 -S -o - %s \
> +// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
> +// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
> +// RUN:  -target-feature +v8.1a -O3 -S -o - %s \
> +// RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
> +
> +#include <arm_neon.h>
> +
> +// CHECK-LABEL: test_vqrdmlah_s16
> +int16x4_t test_vqrdmlah_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
> +// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
> +  return vqrdmlah_s16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlah_s32
> +int32x2_t test_vqrdmlah_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
> +// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
> +  return vqrdmlah_s32(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlahq_s16
> +int16x8_t test_vqrdmlahq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {
> +// CHECK-ARM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
> +  return vqrdmlahq_s16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlahq_s32
> +int32x4_t test_vqrdmlahq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {
> +// CHECK-ARM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
> +  return vqrdmlahq_s32(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlah_lane_s16
> +int16x4_t test_vqrdmlah_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
> +// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[3]
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h,
> {{v[0-9]+}}.h[3]
> +  return vqrdmlah_lane_s16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlah_lane_s32
> +int32x2_t test_vqrdmlah_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
> +// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[1]
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s,
> {{v[0-9]+}}.s[1]
> +  return vqrdmlah_lane_s32(a, b, c, 1);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlahq_lane_s16
> +int16x8_t test_vqrdmlahq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) {
> +// CHECK-ARM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[3]
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h,
> {{v[0-9]+}}.h[3]
> +  return vqrdmlahq_lane_s16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlahq_lane_s32
> +int32x4_t test_vqrdmlahq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) {
> +// CHECK-ARM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[1]
> +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s,
> {{v[0-9]+}}.s[1]
> +  return vqrdmlahq_lane_s32(a, b, c, 1);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlsh_s16
> +int16x4_t test_vqrdmlsh_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
> +// CHECK-ARM: vqrdmlsh.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
> +  return vqrdmlsh_s16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlsh_s32
> +int32x2_t test_vqrdmlsh_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
> +// CHECK-ARM: vqrdmlsh.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
> +  return vqrdmlsh_s32(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlshq_s16
> +int16x8_t test_vqrdmlshq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {
> +// CHECK-ARM: vqrdmlsh.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
> +  return vqrdmlshq_s16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlshq_s32
> +int32x4_t test_vqrdmlshq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {
> +// CHECK-ARM: vqrdmlsh.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
> +  return vqrdmlshq_s32(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlsh_lane_s16
> +int16x4_t test_vqrdmlsh_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
> +// CHECK-ARM: vqrdmlsh.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[3]
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h,
> {{v[0-9]+}}.h[3]
> +  return vqrdmlsh_lane_s16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlsh_lane_s32
> +int32x2_t test_vqrdmlsh_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
> +// CHECK-ARM: vqrdmlsh.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[1]
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s,
> {{v[0-9]+}}.s[1]
> +  return vqrdmlsh_lane_s32(a, b, c, 1);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlshq_lane_s16
> +int16x8_t test_vqrdmlshq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) {
> +// CHECK-ARM: vqrdmlsh.s16 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[3]
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h,
> {{v[0-9]+}}.h[3]
> +  return vqrdmlshq_lane_s16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vqrdmlshq_lane_s32
> +int32x4_t test_vqrdmlshq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) {
> +// CHECK-ARM: vqrdmlsh.s32 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[1]
> +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s,
> {{v[0-9]+}}.s[1]
> +  return vqrdmlshq_lane_s32(a, b, c, 1);
> +}
> +
>
>
> _______________________________________________
> cfe-commits mailing list
> cfe-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/cfe-commits/attachments/20151129/f34b5bd4/attachment.html>