r242313 - [PPC64] Update tests for vec_sld
Hans Wennborg
hans at chromium.org
Fri Jul 17 09:00:44 PDT 2015
Merged in r242532.
Thanks,
Hans
On Fri, Jul 17, 2015 at 8:47 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> Hi Hans,
>
> I approve this for the release branch.
>
> Thanks again,
> Hal
>
> ----- Original Message -----
>> From: "Bill Schmidt" <wschmidt at linux.vnet.ibm.com>
>> To: cfe-commits at cs.uiuc.edu
>> Sent: Wednesday, July 15, 2015 1:55:02 PM
>> Subject: r242313 - [PPC64] Update tests for vec_sld
>>
>> Author: wschmidt
>> Date: Wed Jul 15 13:55:02 2015
>> New Revision: 242313
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=242313&view=rev
>> Log:
>> [PPC64] Update tests for vec_sld
>>
>> Revision 224297 modified the behavior of vec_sld for little endian so
>> that LLVM will generate the correct corresponding vsldoi instruction.
>> I neglected to update the existing tests, which continued to pass
>> because they were not specific enough. This patch adds enough
>> specificity to the tests to make them useful for BE and LE testing of
>> vec_sld.
>>
>> Modified:
>> cfe/trunk/test/CodeGen/builtins-ppc-altivec.c
>>
>> Modified: cfe/trunk/test/CodeGen/builtins-ppc-altivec.c
>> URL:
>> http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-altivec.c?rev=242313&r1=242312&r2=242313&view=diff
>> ==============================================================================
>> --- cfe/trunk/test/CodeGen/builtins-ppc-altivec.c (original)
>> +++ cfe/trunk/test/CodeGen/builtins-ppc-altivec.c Wed Jul 15 13:55:02
>> 2015
>> @@ -3307,81 +3307,225 @@ void test6() {
>>
>> /* vec_sld */
>> res_vsc = vec_sld(vsc, vsc, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vuc = vec_sld(vuc, vuc, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vs = vec_sld(vs, vs, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vus = vec_sld(vus, vus, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vbs = vec_sld(vbs, vbs, 0);
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> // CHECK: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
>> // CHECK: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
>> // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]],
>> <4 x i32> [[T2]], <16 x i8>
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: xor <16 x i8>
>> // CHECK-LE: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
>> // CHECK-LE: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
>> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32>
>> [[T1]], <4 x i32> [[T2]], <16 x i8>
>>
>> res_vp = vec_sld(vp, vp, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vi = vec_sld(vi, vi, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vui = vec_sld(vui, vui, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vbi = vec_sld(vbi, vbi, 0);
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{.+}},
>> <4 x i32> {{.+}}, <16 x i8>
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: xor <16 x i8>
>> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32>
>> {{.+}}, <4 x i32> {{.+}}, <16 x i8>
>>
>> res_vf = vec_sld(vf, vf, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vsc = vec_vsldoi(vsc, vsc, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vuc = vec_vsldoi(vuc, vuc, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vs = vec_vsldoi(vs, vs, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vus = vec_vsldoi(vus, vus, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vp = vec_vsldoi(vp, vp, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vi = vec_vsldoi(vi, vi, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vui = vec_vsldoi(vui, vui, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> res_vf = vec_vsldoi(vf, vf, 0);
>> -// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
>> +// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
>> +// CHECK: @llvm.ppc.altivec.vperm
>> +// CHECK-LE: sub nsw i32 16
>> +// CHECK-LE: sub nsw i32 17
>> +// CHECK-LE: sub nsw i32 18
>> +// CHECK-LE: sub nsw i32 31
>> // CHECK-LE: @llvm.ppc.altivec.vperm
>>
>> /* vec_sll */
>>
>>
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>>
>
> --
> Hal Finkel
> Assistant Computational Scientist
> Leadership Computing Facility
> Argonne National Laboratory
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