[PATCH] [ARM/AArch64] Add ACLE special register intrinsics (10.1)

[Renato Golin]

Bradley,

read/write register are only lowered to movs in the backend, so you could, in theory lower your special register naming to mrs/msr or whatever else you need. You'd only need to allow Clang to recognise that syntax as register names, as for now, it only recognise what's in some tablegen files, I believe.

If that doesn't work, a new builtin with similar syntax and usage would be ok, and you cna use the clang/llvm patches for the named registers as a guide. I've split the warning/error messages on Clang and LLVM, so that we could help the user as much as possible as soon as possible. It should be ok to do the same in your case.

cheers,
--renato

http://reviews.llvm.org/D6247