[PATCH] ARM: add support for QBIT

[Tim Northover]

================
Comment at: lib/Headers/arm_acle.h:121
@@ +120,3 @@
+__set_saturation_occurred(int occurred) {
+  __asm__ __volatile__ ("msr cpsr_q, %0" : : "r" (occurred));
+}
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rengolin wrote:
> t.p.northover wrote:
> > This also doesn't seem to do what ACLE says: set the Q flag based on the LSB of the input.
> > 
> > Also, I don't think "cpsr_q" exists, does it? Both the v7A and v7M descriptions I've found lump it in with NZCV (i.e. "cpsr_nzcvq"). Which probably means the assembly should be marked as clobbering CPSR too.
> I may be wrong, but I think you need to mrs first to get the bit pattern, change this value based on (occurred != 0) shifted to the right place and writing it back with msr, or you'll end up writing zeroes to the other flags. Or is that only the case with registers?
That would preserve NZCV and allow LLVM more optimisation freedom, but at the cost of a more expensive __set_saturation_occurred.

As long as LLVM's aware that we *have* clobbered NZCV (slightly confusingly tracked as CPSR in the 32-bit backend) it should work either way.

Of course, we don't actually model Q now, so we're not making the required guarantees anyway (I think LLVM would consider itself free to move a QADD past these no matter what we do, for example).

http://reviews.llvm.org/D6107