[PATCH] ARM: add support for QBIT

Tim Northover t.p.northover at gmail.com
Tue Nov 4 12:40:21 PST 2014

Hi Saleem,

I don't think these are quite right yet...

Comment at: lib/Headers/arm_acle.h:116
@@ +115,3 @@
+  __asm__ __volatile__("mrs %0, cpsr" : "=r"(cpsr));
+  return cpsr & 0x08000000;
I think ACLE says this function should return 1 when the flag is set.

Comment at: lib/Headers/arm_acle.h:121
@@ +120,3 @@
+__set_saturation_occurred(int occurred) {
+  __asm__ __volatile__ ("msr cpsr_q, %0" : : "r" (occurred));
This also doesn't seem to do what ACLE says: set the Q flag based on the LSB of the input.

Also, I don't think "cpsr_q" exists, does it? Both the v7A and v7M descriptions I've found lump it in with NZCV (i.e. "cpsr_nzcvq"). Which probably means the assembly should be marked as clobbering CPSR too.


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