[PATCH] [PowerPC] Initial VSX intrinsic support, with min/max for vector double
wschmidt at linux.vnet.ibm.com
Thu Oct 23 16:34:10 PDT 2014
Hi hfinkel, seurer, echristo,
Now that we have initial support for VSX, we can begin adding intrinsics for programmer access to VSX instructions. This patch performs the necessary enablement in the front end, and tests it by implementing intrinsics for minimum and maximum using the vector double data type.
The main change in the front end is to no longer disallow "vector" and "double" in the same declaration (lib/Sema/DeclSpec.cpp), but "vector" and "long double" must still be disallowed. The new intrinsics are accessed via vec_max and vec_min with changes in lib/Headers/altivec.h. Note that for v4f32, we already access corresponding VMX builtins, but with VSX enabled we should use the forms that allow all 64 vector registers.
The new builtins are defined in include/clang/Basic/BuiltinsPPC.def.
I've added a new test as test/CodeGen/builtins-ppc-vsx.c that is similar to, but much smaller than, builtins-ppc-altivec.c. This is intended to grow substantially over time, and allows us to test VSX IR generation without duplicating CHECK lines for the existing bazillion Altivec tests.
Since vector double is not legal, I've removed the expected error messages saying that it isn't from the existing tests test/Parser/altivec.c and test/Parser/cxx-altivec.cpp; and I've changed the expected error messages for 'vector long double'.
There is a companion patch for LLVM that will be reviewed separately; see http://reviews.llvm.org/D5948.
echristo: I added you as a reviewer, but please feel free to nominate a front-end personage to take your place. I'm not sure who should review the decl-spec parsing changes.
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