r196199 - AArch64: Add missing scalar pair intrinsics.
Hao Liu
Hao.Liu at arm.com
Mon Dec 2 19:40:09 PST 2013
Author: haoliu
Date: Mon Dec 2 21:40:08 2013
New Revision: 196199
URL: http://llvm.org/viewvc/llvm-project?rev=196199&view=rev
Log:
AArch64: Add missing scalar pair intrinsics.
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s".
Modified:
cfe/trunk/include/clang/Basic/arm_neon.td
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
Modified: cfe/trunk/include/clang/Basic/arm_neon.td
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=196199&r1=196198&r2=196199&view=diff
==============================================================================
--- cfe/trunk/include/clang/Basic/arm_neon.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon.td Mon Dec 2 21:40:08 2013
@@ -779,7 +779,7 @@ def FMINNMP : SInst<"vpminnm", "ddd", "f
////////////////////////////////////////////////////////////////////////////////
// Pairwise Addition
// With additional Qc Qs Qi QUc QUs QUi Qf Qd types.
-def ADDP : IInst<"vpadd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">;
+def ADDP : IInst<"vpadd", "ddd", "csiUcUsUifQcQsQiQlQUcQUsQUiQUlQfQd">;
////////////////////////////////////////////////////////////////////////////////
// Shifts by constant
@@ -951,11 +951,11 @@ def VMULX_LANEQ : IOpInst<"vmulx_laneq",
////////////////////////////////////////////////////////////////////////////////
// Across vectors class
def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">;
-def VMAXV : SInst<"vmaxv", "sd", "csiUcUsUiQcQsQiQUcQUsQUiQf">;
-def VMINV : SInst<"vminv", "sd", "csiUcUsUiQcQsQiQUcQUsQUiQf">;
-def VADDV : SInst<"vaddv", "sd", "csiUcUsUiQcQsQiQUcQUsQUi">;
-def FMAXNMV : SInst<"vmaxnmv", "sd", "Qf">;
-def FMINNMV : SInst<"vminnmv", "sd", "Qf">;
+def VMAXV : SInst<"vmaxv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
+def VMINV : SInst<"vminv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
+def VADDV : SInst<"vaddv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">;
+def FMAXNMV : SInst<"vmaxnmv", "sd", "fQfQd">;
+def FMINNMV : SInst<"vminnmv", "sd", "fQfQd">;
////////////////////////////////////////////////////////////////////////////////
// Newly added Vector Extract for f64
@@ -1104,7 +1104,7 @@ def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_
////////////////////////////////////////////////////////////////////////////////
// Scalar Reduce Pairwise Addition (Scalar and Floating Point)
-def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHd">;
+def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHdSHUl">;
////////////////////////////////////////////////////////////////////////////////
// Scalar Reduce Floating Point Pairwise Max/Min
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=196199&r1=196198&r2=196199&view=diff
==============================================================================
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Mon Dec 2 21:40:08 2013
@@ -1985,6 +1985,7 @@ static Value *EmitAArch64ScalarBuiltinEx
s = "vqrshlu"; OverloadInt = true; break;
// Scalar Reduce Pairwise Add
case AArch64::BI__builtin_neon_vpaddd_s64:
+ case AArch64::BI__builtin_neon_vpaddd_u64:
Int = Intrinsic::aarch64_neon_vpadd; s = "vpadd";
break;
case AArch64::BI__builtin_neon_vpadds_f32:
@@ -2069,23 +2070,36 @@ static Value *EmitAArch64ScalarBuiltinEx
case AArch64::BI__builtin_neon_vaddvq_s8:
case AArch64::BI__builtin_neon_vaddvq_s16:
case AArch64::BI__builtin_neon_vaddvq_s32:
+ case AArch64::BI__builtin_neon_vaddvq_s64:
case AArch64::BI__builtin_neon_vaddv_u8:
case AArch64::BI__builtin_neon_vaddv_u16:
case AArch64::BI__builtin_neon_vaddvq_u8:
case AArch64::BI__builtin_neon_vaddvq_u16:
case AArch64::BI__builtin_neon_vaddvq_u32:
+ case AArch64::BI__builtin_neon_vaddvq_u64:
+ case AArch64::BI__builtin_neon_vaddv_f32:
+ case AArch64::BI__builtin_neon_vaddvq_f32:
+ case AArch64::BI__builtin_neon_vaddvq_f64:
Int = Intrinsic::aarch64_neon_vaddv;
AcrossVec = true; ExtendEle = false; s = "vaddv"; break;
+ case AArch64::BI__builtin_neon_vmaxv_f32:
case AArch64::BI__builtin_neon_vmaxvq_f32:
+ case AArch64::BI__builtin_neon_vmaxvq_f64:
Int = Intrinsic::aarch64_neon_vmaxv;
AcrossVec = true; ExtendEle = false; s = "vmaxv"; break;
+ case AArch64::BI__builtin_neon_vminv_f32:
case AArch64::BI__builtin_neon_vminvq_f32:
+ case AArch64::BI__builtin_neon_vminvq_f64:
Int = Intrinsic::aarch64_neon_vminv;
AcrossVec = true; ExtendEle = false; s = "vminv"; break;
+ case AArch64::BI__builtin_neon_vmaxnmv_f32:
case AArch64::BI__builtin_neon_vmaxnmvq_f32:
+ case AArch64::BI__builtin_neon_vmaxnmvq_f64:
Int = Intrinsic::aarch64_neon_vmaxnmv;
AcrossVec = true; ExtendEle = false; s = "vmaxnmv"; break;
+ case AArch64::BI__builtin_neon_vminnmv_f32:
case AArch64::BI__builtin_neon_vminnmvq_f32:
+ case AArch64::BI__builtin_neon_vminnmvq_f64:
Int = Intrinsic::aarch64_neon_vminnmv;
AcrossVec = true; ExtendEle = false; s = "vminnmv"; break;
// Scalar Integer Saturating Doubling Multiply Half High
Modified: cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=196199&r1=196198&r2=196199&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c (original)
+++ cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Mon Dec 2 21:40:08 2013
@@ -11272,3 +11272,100 @@ int64x1_t test_vneg_s64(int64x1_t a) {
return vneg_s64(a);
// CHECK: neg d{{[0-9]+}}, d{{[0-9]+}}
}
+
+float32_t test_vaddv_f32(float32x2_t a) {
+ // CHECK-LABEL: test_vaddv_f32
+ return vaddv_f32(a);
+ // CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
+}
+
+float32_t test_vaddvq_f32(float32x4_t a) {
+ // CHECK-LABEL: test_vaddvq_f32
+ return vaddvq_f32(a);
+ // CHECK: faddp {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+ // CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
+}
+
+float64_t test_vaddvq_f64(float64x2_t a) {
+ // CHECK-LABEL: test_vaddvq_f64
+ return vaddvq_f64(a);
+ // CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
+}
+
+float32_t test_vmaxv_f32(float32x2_t a) {
+ // CHECK-LABEL: test_vmaxv_f32
+ return vmaxv_f32(a);
+ // CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
+}
+
+float64_t test_vmaxvq_f64(float64x2_t a) {
+ // CHECK-LABEL: test_vmaxvq_f64
+ return vmaxvq_f64(a);
+ // CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
+}
+
+float32_t test_vminv_f32(float32x2_t a) {
+ // CHECK-LABEL: test_vminv_f32
+ return vminv_f32(a);
+ // CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
+}
+
+float64_t test_vminvq_f64(float64x2_t a) {
+ // CHECK-LABEL: test_vminvq_f64
+ return vminvq_f64(a);
+ // CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
+}
+
+float64_t test_vmaxnmvq_f64(float64x2_t a) {
+ // CHECK-LABEL: test_vmaxnmvq_f64
+ return vmaxnmvq_f64(a);
+ // CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
+}
+
+float32_t test_vmaxnmv_f32(float32x2_t a) {
+ // CHECK-LABEL: test_vmaxnmv_f32
+ return vmaxnmv_f32(a);
+ // CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
+}
+
+float64_t test_vminnmvq_f64(float64x2_t a) {
+ // CHECK-LABEL: test_vminnmvq_f64
+ return vminnmvq_f64(a);
+ // CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
+}
+
+float32_t test_vminnmv_f32(float32x2_t a) {
+ // CHECK-LABEL: test_vminnmv_f32
+ return vminnmv_f32(a);
+ // CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
+}
+
+int64x2_t test_vpaddq_s64(int64x2_t a, int64x2_t b) {
+ // CHECK-LABEL: test_vpaddq_s64
+ return vpaddq_s64(a, b);
+ // CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+}
+
+uint64x2_t test_vpaddq_u64(uint64x2_t a, uint64x2_t b) {
+ // CHECK-LABEL: test_vpaddq_u64
+ return vpaddq_u64(a, b);
+ // CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+}
+
+uint64_t test_vpaddd_u64(uint64x2_t a) {
+ // CHECK-LABEL: test_vpaddd_u64
+ return vpaddd_u64(a);
+ // CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
+}
+
+int64_t test_vaddvq_s64(int64x2_t a) {
+ // CHECK-LABEL: test_vaddvq_s64
+ return vaddvq_s64(a);
+ // CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
+}
+
+uint64_t test_vaddvq_u64(uint64x2_t a) {
+ // CHECK-LABEL: test_vaddvq_u64
+ return vaddvq_u64(a);
+ // CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
+}
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