r194476 - [mips][msa] Enable inlinse assembly for MSA.

[Daniel Sanders]

Author: dsanders
Date: Tue Nov 12 06:56:01 2013
New Revision: 194476

URL: http://llvm.org/viewvc/llvm-project?rev=194476&view=rev
Log:
[mips][msa] Enable inlinse assembly for MSA.

Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
  asm ("ldi.w %w0, 1", "=f"(result));

Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.

MSA registers (including control registers) are supported in clobber lists.


Modified:
    cfe/trunk/lib/Basic/Targets.cpp
    cfe/trunk/test/CodeGen/mips-clobber-reg.c
    cfe/trunk/test/CodeGen/mips-inline-asm-modifiers.c

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=194476&r1=194475&r2=194476&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Tue Nov 12 06:56:01 2013
@@ -4916,7 +4916,7 @@ public:
   }
   virtual void getGCCRegNames(const char * const *&Names,
                               unsigned &NumNames) const {
-    static const char * const GCCRegNames[] = {
+    static const char *const GCCRegNames[] = {
       // CPU register names
       // Must match second column of GCCRegAliases
       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
@@ -4930,7 +4930,15 @@ public:
       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
       // Hi/lo and condition register names
       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
-      "$fcc5","$fcc6","$fcc7"
+      "$fcc5","$fcc6","$fcc7",
+      // MSA register names
+      "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
+      "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
+      "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
+      "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
+      // MSA control register names
+      "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
+      "$msarequest", "$msamap", "$msaunmap"
     };
     Names = GCCRegNames;
     NumNames = llvm::array_lengthof(GCCRegNames);

Modified: cfe/trunk/test/CodeGen/mips-clobber-reg.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-clobber-reg.c?rev=194476&r1=194475&r2=194476&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/mips-clobber-reg.c (original)
+++ cfe/trunk/test/CodeGen/mips-clobber-reg.c Tue Nov 12 06:56:01 2013
@@ -7,6 +7,8 @@
     Includes:
     - GPR
     - FPU
+    - MSA
+
     Any bad names will make the frontend choke.
  */
 
@@ -113,4 +115,36 @@ main()
     __asm__ __volatile__ ("fadd.s $f30,77":::"$f30");
     __asm__ __volatile__ ("fadd.s $f31,77":::"$f31");
 
+    __asm__ __volatile__ ("ldi.w $w0,77":::"$w0");
+    __asm__ __volatile__ ("ldi.w $w1,77":::"$w1");
+    __asm__ __volatile__ ("ldi.w $w2,77":::"$w2");
+    __asm__ __volatile__ ("ldi.w $w3,77":::"$w3");
+    __asm__ __volatile__ ("ldi.w $w4,77":::"$w4");
+    __asm__ __volatile__ ("ldi.w $w5,77":::"$w5");
+    __asm__ __volatile__ ("ldi.w $w6,77":::"$w6");
+    __asm__ __volatile__ ("ldi.w $w7,77":::"$w7");
+    __asm__ __volatile__ ("ldi.w $w8,77":::"$w8");
+    __asm__ __volatile__ ("ldi.w $w9,77":::"$w9");
+    __asm__ __volatile__ ("ldi.w $w10,77":::"$w10");
+    __asm__ __volatile__ ("ldi.w $w11,77":::"$w10");
+    __asm__ __volatile__ ("ldi.w $w12,77":::"$w12");
+    __asm__ __volatile__ ("ldi.w $w13,77":::"$w13");
+    __asm__ __volatile__ ("ldi.w $w14,77":::"$w14");
+    __asm__ __volatile__ ("ldi.w $w15,77":::"$w15");
+    __asm__ __volatile__ ("ldi.w $w16,77":::"$w16");
+    __asm__ __volatile__ ("ldi.w $w17,77":::"$w17");
+    __asm__ __volatile__ ("ldi.w $w18,77":::"$w18");
+    __asm__ __volatile__ ("ldi.w $w19,77":::"$w19");
+    __asm__ __volatile__ ("ldi.w $w20,77":::"$w20");
+    __asm__ __volatile__ ("ldi.w $w21,77":::"$w21");
+    __asm__ __volatile__ ("ldi.w $w22,77":::"$w22");
+    __asm__ __volatile__ ("ldi.w $w23,77":::"$w23");
+    __asm__ __volatile__ ("ldi.w $w24,77":::"$w24");
+    __asm__ __volatile__ ("ldi.w $w25,77":::"$w25");
+    __asm__ __volatile__ ("ldi.w $w26,77":::"$w26");
+    __asm__ __volatile__ ("ldi.w $w27,77":::"$w27");
+    __asm__ __volatile__ ("ldi.w $w28,77":::"$w28");
+    __asm__ __volatile__ ("ldi.w $w29,77":::"$w29");
+    __asm__ __volatile__ ("ldi.w $w30,77":::"$w30");
+    __asm__ __volatile__ ("ldi.w $w31,77":::"$w31");
 }

Modified: cfe/trunk/test/CodeGen/mips-inline-asm-modifiers.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-inline-asm-modifiers.c?rev=194476&r1=194475&r2=194476&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/mips-inline-asm-modifiers.c (original)
+++ cfe/trunk/test/CodeGen/mips-inline-asm-modifiers.c Tue Nov 12 06:56:01 2013
@@ -5,12 +5,16 @@
 
 int printf(const char*, ...);
 
+typedef int v4i32 __attribute__((vector_size(16)));
+
   // CHECK: %{{[0-9]+}} = call i32 asm ".set noreorder;\0Alw    $0,$1;\0A.set reorder;\0A", "=r,*m"(i32* getelementptr inbounds ([8 x i32]* @b, i32 {{[0-9]+}}, i32 {{[0-9]+}})) #2,
   // CHECK: %{{[0-9]+}} = call i32 asm "lw    $0,${1:D};\0A", "=r,*m"(i32* getelementptr inbounds ([8 x i32]* @b, i32 {{[0-9]+}}, i32 {{[0-9]+}})) #2,
+  // CHECK: %{{[0-9]+}} = call <4 x i32> asm "ldi.w ${0:w},1", "=f"
 int b[8] = {0,1,2,3,4,5,6,7};
 int  main()
 {
   int i;
+  v4i32 v4i32_r;
 
   // The first word. Notice, no 'D'
   {asm (
@@ -29,6 +33,9 @@ int  main()
   : "m" (*(b+4))
   );}
 
+  // MSA registers
+  {asm ("ldi.w %w0,1" : "=f" (v4i32_r));}
+
   printf("%d\n",i);
 
   return 1;