[PATCH] Implement aarch64 neon instruction class SIMD Perm - Clang

[Jiangning Liu]

Hi Tim,

Are you talking about the intrinsics without digit suffix like vuzp_s8?
They looks like legacy for me. If yes, I think this is already covered. I
have test like the followings,

int8x8x2_t test_vuzp_s8(int8x8_t a, int8x8_t b) {
  // CHECK: test_vuzp_s8
  return vuzp_s8(a, b);
  // CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
  // CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
}

Thanks,
-Jiangning



2013/11/6 Tim Northover <t.p.northover at gmail.com>

>
>   Hi Jiangning,
>
>   I've got one question (well, stated as a comment) about this Clang stuff.
>
>   Cheers.
>
>   Tim.
>
>
> ================
> Comment at: lib/CodeGen/CGBuiltin.cpp:2374-2375
> @@ -2373,1 +2373,4 @@
>    // in aarch64-neon-intrinsics.c so far.
> +  case AArch64::BI__builtin_neon_vuzp_v:
> +    return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vuzp_v, E);
> +  case AArch64::BI__builtin_neon_vuzpq_v:
> ----------------
> If I'm reading correctly these cases (the legacy ARM zip/uzp/trn
> intrinsics) are neither tested in this patch nor implemented on the LLVM
> side.
>
>
> http://llvm-reviews.chandlerc.com/D2075
>



-- 
Thanks,
-Jiangning
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