r193118 - [AArch64] Add the constraint to NEON scalar mla/mls instructions.

[Chad Rosier]

Author: mcrosier
Date: Mon Oct 21 15:12:01 2013
New Revision: 193118

URL: http://llvm.org/viewvc/llvm-project?rev=193118&view=rev
Log:
[AArch64] Add the constraint to NEON scalar mla/mls instructions.

Modified:
    cfe/trunk/include/clang/Basic/arm_neon.td
    cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c

Modified: cfe/trunk/include/clang/Basic/arm_neon.td
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=193118&r1=193117&r2=193118&view=diff
==============================================================================
--- cfe/trunk/include/clang/Basic/arm_neon.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon.td Mon Oct 21 15:12:01 2013
@@ -882,11 +882,11 @@ def SCALAR_USQADD : SInst<"vsqadd", "sss
 
 ////////////////////////////////////////////////////////////////////////////////
 // Signed Saturating Doubling Multiply-Add Long
-def SCALAR_SQDMLAL : SInst<"vqdmlal", "rss", "SsSi">;
+def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Signed Saturating Doubling Multiply-Subtract Long
-def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rss", "SsSi">;
+def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Signed Saturating Doubling Multiply Long

Modified: cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=193118&r1=193117&r2=193118&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c (original)
+++ cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Mon Oct 21 15:12:01 2013
@@ -7226,28 +7226,28 @@ uint64_t test_vsqaddd_u64(uint64_t a, ui
   return (uint64_t)vsqaddd_u64(a, b);
 }
 
-int32_t test_vqdmlalh_s16(int16_t a, int16_t b) {
+int32_t test_vqdmlalh_s16(int32_t a, int16_t b, int16_t c) {
 // CHECK: test_vqdmlalh_s16
 // CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
-  return (int32_t)vqdmlalh_s16(a, b);
+  return (int32_t)vqdmlalh_s16(a, b, c);
 }
 
-int64_t test_vqdmlals_s32(int32_t a, int32_t b) {
+int64_t test_vqdmlals_s32(int64_t a, int32_t b, int32_t c) {
 // CHECK: test_vqdmlals_s32
 // CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
-  return (int64_t)vqdmlals_s32(a, b);
+  return (int64_t)vqdmlals_s32(a, b, c);
 }
 
-int32_t test_vqdmlslh_s16(int16_t a, int16_t b) {
+int32_t test_vqdmlslh_s16(int32_t a, int16_t b, int16_t c) {
 // CHECK: test_vqdmlslh_s16
 // CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
-  return (int32_t)vqdmlslh_s16(a, b);
+  return (int32_t)vqdmlslh_s16(a, b, c);
 }
 
-int64_t test_vqdmlsls_s32(int32_t a, int32_t b) {
+int64_t test_vqdmlsls_s32(int64_t a, int32_t b, int32_t c) {
 // CHECK: test_vqdmlsls_s32
 // CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
-  return (int64_t)vqdmlsls_s32(a, b);
+  return (int64_t)vqdmlsls_s32(a, b, c);
 }
 
 int32_t test_vqdmullh_s16(int16_t a, int16_t b) {