[PATCH] [2/2] Add PRFCHW feature to a few AMD processors

[Yunzhong Gao]

ygao added you to the CC list for the revision "[2/2] Add PRFCHW feature to a few AMD processors".

Hi,
This patch enables the 3dNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Could someone take a look whether this is good to go in?
Thanks,
- Gao.

http://llvm-reviews.chandlerc.com/D1934

Files:
  lib/Basic/Targets.cpp
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Basic/Targets.cpp
===================================================================
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2120,6 +2120,7 @@
     setFeatureEnabledImpl(Features, "cx16", true);
     setFeatureEnabledImpl(Features, "lzcnt", true);
     setFeatureEnabledImpl(Features, "popcnt", true);
+    setFeatureEnabledImpl(Features, "prfchw", true);
     break;
   case CK_BTVER2:
     setFeatureEnabledImpl(Features, "avx", true);
@@ -2127,6 +2128,7 @@
     setFeatureEnabledImpl(Features, "lzcnt", true);
     setFeatureEnabledImpl(Features, "aes", true);
     setFeatureEnabledImpl(Features, "pclmul", true);
+    setFeatureEnabledImpl(Features, "prfchw", true);
     setFeatureEnabledImpl(Features, "bmi", true);
     setFeatureEnabledImpl(Features, "f16c", true);
     setFeatureEnabledImpl(Features, "cx16", true);
@@ -2136,6 +2138,7 @@
     setFeatureEnabledImpl(Features, "lzcnt", true);
     setFeatureEnabledImpl(Features, "aes", true);
     setFeatureEnabledImpl(Features, "pclmul", true);
+    setFeatureEnabledImpl(Features, "prfchw", true);
     setFeatureEnabledImpl(Features, "cx16", true);
     break;
   case CK_BDVER2:
@@ -2143,6 +2146,7 @@
     setFeatureEnabledImpl(Features, "lzcnt", true);
     setFeatureEnabledImpl(Features, "aes", true);
     setFeatureEnabledImpl(Features, "pclmul", true);
+    setFeatureEnabledImpl(Features, "prfchw", true);
     setFeatureEnabledImpl(Features, "bmi", true);
     setFeatureEnabledImpl(Features, "fma", true);
     setFeatureEnabledImpl(Features, "f16c", true);
Index: test/Preprocessor/predefined-arch-macros.c
===================================================================
--- test/Preprocessor/predefined-arch-macros.c
+++ test/Preprocessor/predefined-arch-macros.c
@@ -1166,6 +1166,7 @@
 // CHECK_BTVER1_M32: #define __LZCNT__ 1
 // CHECK_BTVER1_M32: #define __MMX__ 1
 // CHECK_BTVER1_M32: #define __POPCNT__ 1
+// CHECK_BTVER1_M32: #define __PRFCHW__ 1
 // CHECK_BTVER1_M32: #define __SSE2_MATH__ 1
 // CHECK_BTVER1_M32: #define __SSE2__ 1
 // CHECK_BTVER1_M32: #define __SSE3__ 1
@@ -1186,6 +1187,7 @@
 // CHECK_BTVER1_M64: #define __LZCNT__ 1
 // CHECK_BTVER1_M64: #define __MMX__ 1
 // CHECK_BTVER1_M64: #define __POPCNT__ 1
+// CHECK_BTVER1_M64: #define __PRFCHW__ 1
 // CHECK_BTVER1_M64: #define __SSE2_MATH__ 1
 // CHECK_BTVER1_M64: #define __SSE2__ 1
 // CHECK_BTVER1_M64: #define __SSE3__ 1
@@ -1210,6 +1212,7 @@
 // CHECK_BTVER2_M32: #define __LZCNT__ 1
 // CHECK_BTVER2_M32: #define __MMX__ 1
 // CHECK_BTVER2_M32: #define __POPCNT__ 1
+// CHECK_BTVER2_M32: #define __PRFCHW__ 1
 // CHECK_BTVER2_M32: #define __SSE2_MATH__ 1
 // CHECK_BTVER2_M32: #define __SSE2__ 1
 // CHECK_BTVER2_M32: #define __SSE3__ 1
@@ -1232,6 +1235,7 @@
 // CHECK_BTVER2_M64: #define __LZCNT__ 1
 // CHECK_BTVER2_M64: #define __MMX__ 1
 // CHECK_BTVER2_M64: #define __POPCNT__ 1
+// CHECK_BTVER2_M64: #define __PRFCHW__ 1
 // CHECK_BTVER2_M64: #define __SSE2_MATH__ 1
 // CHECK_BTVER2_M64: #define __SSE2__ 1
 // CHECK_BTVER2_M64: #define __SSE3__ 1
@@ -1258,6 +1262,7 @@
 // CHECK_BDVER1_M32: #define __MMX__ 1
 // CHECK_BDVER1_M32: #define __PCLMUL__ 1
 // CHECK_BDVER1_M32: #define __POPCNT__ 1
+// CHECK_BDVER1_M32: #define __PRFCHW__ 1
 // CHECK_BDVER1_M32: #define __SSE2_MATH__ 1
 // CHECK_BDVER1_M32: #define __SSE2__ 1
 // CHECK_BDVER1_M32: #define __SSE3__ 1
@@ -1285,6 +1290,7 @@
 // CHECK_BDVER1_M64: #define __MMX__ 1
 // CHECK_BDVER1_M64: #define __PCLMUL__ 1
 // CHECK_BDVER1_M64: #define __POPCNT__ 1
+// CHECK_BDVER1_M64: #define __PRFCHW__ 1
 // CHECK_BDVER1_M64: #define __SSE2_MATH__ 1
 // CHECK_BDVER1_M64: #define __SSE2__ 1
 // CHECK_BDVER1_M64: #define __SSE3__ 1
@@ -1317,6 +1323,7 @@
 // CHECK_BDVER2_M32: #define __MMX__ 1
 // CHECK_BDVER2_M32: #define __PCLMUL__ 1
 // CHECK_BDVER2_M32: #define __POPCNT__ 1
+// CHECK_BDVER2_M32: #define __PRFCHW__ 1
 // CHECK_BDVER2_M32: #define __SSE2_MATH__ 1
 // CHECK_BDVER2_M32: #define __SSE2__ 1
 // CHECK_BDVER2_M32: #define __SSE3__ 1
@@ -1348,6 +1355,7 @@
 // CHECK_BDVER2_M64: #define __MMX__ 1
 // CHECK_BDVER2_M64: #define __PCLMUL__ 1
 // CHECK_BDVER2_M64: #define __POPCNT__ 1
+// CHECK_BDVER2_M64: #define __PRFCHW__ 1
 // CHECK_BDVER2_M64: #define __SSE2_MATH__ 1
 // CHECK_BDVER2_M64: #define __SSE2__ 1
 // CHECK_BDVER2_M64: #define __SSE3__ 1
Index: test/Preprocessor/x86_target_features.c
===================================================================
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -215,3 +215,12 @@
 // RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck --check-prefix=MCX16 %s
 
 // MCX16: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck --check-prefix=PRFCHW %s
+
+// PRFCHW: #define __PRFCHW__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=btver2 -mno-prfchw -x c -E -dM -o - %s | FileCheck --check-prefix=NOPRFCHW %s
+
+// NOPRFCHW-NOT: #define __PRFCHW__ 1
+
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