r190931 - [ARMv8] Add builtins for CRC instructions.
Joey Gouly
joey.gouly at arm.com
Wed Sep 18 03:07:09 PDT 2013
Author: joey
Date: Wed Sep 18 05:07:09 2013
New Revision: 190931
URL: http://llvm.org/viewvc/llvm-project?rev=190931&view=rev
Log:
[ARMv8] Add builtins for CRC instructions.
Patch by Bradley Smith!
Added:
cfe/trunk/test/CodeGen/arm-crc32.c
cfe/trunk/test/Preprocessor/arm-target-features.c
Modified:
cfe/trunk/include/clang/Basic/BuiltinsARM.def
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
Modified: cfe/trunk/include/clang/Basic/BuiltinsARM.def
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsARM.def?rev=190931&r1=190930&r2=190931&view=diff
==============================================================================
--- cfe/trunk/include/clang/Basic/BuiltinsARM.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsARM.def Wed Sep 18 05:07:09 2013
@@ -48,6 +48,16 @@ BUILTIN(__builtin_arm_cdp2, "vUiUiUiUiUi
BUILTIN(__builtin_arm_mcrr, "vUiUiUiUiUi", "")
BUILTIN(__builtin_arm_mcrr2, "vUiUiUiUiUi", "")
+// CRC32
+BUILTIN(__builtin_arm_crc32b, "UiUiUc", "nc")
+BUILTIN(__builtin_arm_crc32cb, "UiUiUc", "nc")
+BUILTIN(__builtin_arm_crc32h, "UiUiUs", "nc")
+BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc")
+BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc")
+BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc")
+
// NEON
#define GET_NEON_BUILTINS
#include "clang/Basic/arm_neon.inc"
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=190931&r1=190930&r2=190931&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Wed Sep 18 05:07:09 2013
@@ -3829,6 +3829,9 @@ public:
// when Neon instructions are actually available.
if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
Builder.defineMacro("__ARM_NEON__");
+
+ if (CPUArch.startswith("8"))
+ Builder.defineMacro("__ARM_FEATURE_CRC32");
}
virtual void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const {
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=190931&r1=190930&r2=190931&view=diff
==============================================================================
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Wed Sep 18 05:07:09 2013
@@ -2153,6 +2153,49 @@ Value *CodeGenFunction::EmitARMBuiltinEx
return Builder.CreateCall(F);
}
+ // CRC32
+ Intrinsic::ID CRCIntrinsicID = Intrinsic::not_intrinsic;
+ switch (BuiltinID) {
+ case ARM::BI__builtin_arm_crc32b:
+ CRCIntrinsicID = Intrinsic::arm_crc32b; break;
+ case ARM::BI__builtin_arm_crc32cb:
+ CRCIntrinsicID = Intrinsic::arm_crc32cb; break;
+ case ARM::BI__builtin_arm_crc32h:
+ CRCIntrinsicID = Intrinsic::arm_crc32h; break;
+ case ARM::BI__builtin_arm_crc32ch:
+ CRCIntrinsicID = Intrinsic::arm_crc32ch; break;
+ case ARM::BI__builtin_arm_crc32w:
+ case ARM::BI__builtin_arm_crc32d:
+ CRCIntrinsicID = Intrinsic::arm_crc32w; break;
+ case ARM::BI__builtin_arm_crc32cw:
+ case ARM::BI__builtin_arm_crc32cd:
+ CRCIntrinsicID = Intrinsic::arm_crc32cw; break;
+ }
+
+ if (CRCIntrinsicID != Intrinsic::not_intrinsic) {
+ Value *Arg0 = EmitScalarExpr(E->getArg(0));
+ Value *Arg1 = EmitScalarExpr(E->getArg(1));
+
+ // crc32{c,}d intrinsics are implemnted as two calls to crc32{c,}w
+ // intrinsics, hence we need different codegen for these cases.
+ if (BuiltinID == ARM::BI__builtin_arm_crc32d ||
+ BuiltinID == ARM::BI__builtin_arm_crc32cd) {
+ Value *C1 = llvm::ConstantInt::get(Int64Ty, 32);
+ Value *Arg1a = Builder.CreateTruncOrBitCast(Arg1, Int32Ty);
+ Value *Arg1b = Builder.CreateLShr(Arg1, C1);
+ Arg1b = Builder.CreateTruncOrBitCast(Arg1b, Int32Ty);
+
+ Function *F = CGM.getIntrinsic(CRCIntrinsicID);
+ Value *Res = Builder.CreateCall2(F, Arg0, Arg1a);
+ return Builder.CreateCall2(F, Res, Arg1b);
+ } else {
+ Arg1 = Builder.CreateZExtOrBitCast(Arg1, Int32Ty);
+
+ Function *F = CGM.getIntrinsic(CRCIntrinsicID);
+ return Builder.CreateCall2(F, Arg0, Arg1);
+ }
+ }
+
SmallVector<Value*, 4> Ops;
llvm::Value *Align = 0;
for (unsigned i = 0, e = E->getNumArgs() - 1; i != e; i++) {
Added: cfe/trunk/test/CodeGen/arm-crc32.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-crc32.c?rev=190931&view=auto
==============================================================================
--- cfe/trunk/test/CodeGen/arm-crc32.c (added)
+++ cfe/trunk/test/CodeGen/arm-crc32.c Wed Sep 18 05:07:09 2013
@@ -0,0 +1,63 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang_cc1 -triple armv8-none-linux-gnueabi \
+// RUN: -O3 -S -emit-llvm -o - %s | FileCheck %s
+
+int crc32b(int a, char b)
+{
+ return __builtin_arm_crc32b(a,b);
+// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
+// CHECK: call i32 @llvm.arm.crc32b(i32 %a, i32 [[T0]])
+}
+
+int crc32cb(int a, char b)
+{
+ return __builtin_arm_crc32cb(a,b);
+// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
+// CHECK: call i32 @llvm.arm.crc32cb(i32 %a, i32 [[T0]])
+}
+
+int crc32h(int a, short b)
+{
+ return __builtin_arm_crc32h(a,b);
+// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
+// CHECK: call i32 @llvm.arm.crc32h(i32 %a, i32 [[T0]])
+}
+
+int crc32ch(int a, short b)
+{
+ return __builtin_arm_crc32ch(a,b);
+// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
+// CHECK: call i32 @llvm.arm.crc32ch(i32 %a, i32 [[T0]])
+}
+
+int crc32w(int a, int b)
+{
+ return __builtin_arm_crc32w(a,b);
+// CHECK: call i32 @llvm.arm.crc32w(i32 %a, i32 %b)
+}
+
+int crc32cw(int a, int b)
+{
+ return __builtin_arm_crc32cw(a,b);
+// CHECK: call i32 @llvm.arm.crc32cw(i32 %a, i32 %b)
+}
+
+int crc32d(int a, long long b)
+{
+ return __builtin_arm_crc32d(a,b);
+// CHECK: [[T0:%[0-9]+]] = trunc i64 %b to i32
+// CHECK: [[T1:%[0-9]+]] = lshr i64 %b, 32
+// CHECK: [[T2:%[0-9]+]] = trunc i64 [[T1]] to i32
+// CHECK: [[T3:%[0-9]+]] = tail call i32 @llvm.arm.crc32w(i32 %a, i32 [[T0]])
+// CHECK: call i32 @llvm.arm.crc32w(i32 [[T3]], i32 [[T2]])
+}
+
+int crc32cd(int a, long long b)
+{
+ return __builtin_arm_crc32cd(a,b);
+// CHECK: [[T0:%[0-9]+]] = trunc i64 %b to i32
+// CHECK: [[T1:%[0-9]+]] = lshr i64 %b, 32
+// CHECK: [[T2:%[0-9]+]] = trunc i64 [[T1]] to i32
+// CHECK: [[T3:%[0-9]+]] = tail call i32 @llvm.arm.crc32cw(i32 %a, i32 [[T0]])
+// CHECK: call i32 @llvm.arm.crc32cw(i32 [[T3]], i32 [[T2]])
+}
Added: cfe/trunk/test/Preprocessor/arm-target-features.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/arm-target-features.c?rev=190931&view=auto
==============================================================================
--- cfe/trunk/test/Preprocessor/arm-target-features.c (added)
+++ cfe/trunk/test/Preprocessor/arm-target-features.c Wed Sep 18 05:07:09 2013
@@ -0,0 +1,11 @@
+// RUN: %clang -target armv8a-none-linux-gnu -x c -E -dM %s -o - | FileCheck %s
+// CHECK: __ARMEL__ 1
+// CHECK: __ARM_ARCH 8
+// CHECK: __ARM_ARCH_8A__ 1
+// CHECK: __ARM_FEATURE_CRC32 1
+
+// RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-V7 %s
+// CHECK-V7: __ARMEL__ 1
+// CHECK-V7: __ARM_ARCH 7
+// CHECK-V7: __ARM_ARCH_7A__ 1
+// CHECK-NOT-V7: __ARM_FEATURE_CRC32
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