[all-commits] [llvm/llvm-project] 283b4d: [GlobalISel] Add G_VECREDUCE_* opcodes for vector ...

[AE via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 283b4d6ba3119730e1722e8d78974b2c29d2492a
      https://github.com/llvm/llvm-project/commit/283b4d6ba3119730e1722e8d78974b2c29d2492a
  Author: Amara Emerson <amara at apple.com>
  Date:   2020-10-08 (Thu, 08 Oct 2020)

  Changed paths:
    M llvm/docs/GlobalISel/GenericOpcode.rst
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    A llvm/test/MachineVerifier/test_vector_reductions.mir

  Log Message:
  -----------
  [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions.

These mirror the IR and SelectionDAG intrinsics & nodes.

Opcodes added:
G_VECREDUCE_SEQ_FADD
G_VECREDUCE_SEQ_FMUL
G_VECREDUCE_FADD
G_VECREDUCE_FMUL
G_VECREDUCE_FMAX
G_VECREDUCE_FMIN
G_VECREDUCE_ADD
G_VECREDUCE_MUL
G_VECREDUCE_AND
G_VECREDUCE_OR
G_VECREDUCE_XOR
G_VECREDUCE_SMAX
G_VECREDUCE_SMIN
G_VECREDUCE_UMAX
G_VECREDUCE_UMIN

Differential Revision: https://reviews.llvm.org/D88750