[all-commits] [llvm/llvm-project] 764c1b: [RISCV] Scheduler description for Bullet

[Evandro Menezes via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 764c1b7a4db1606438c8daea13c9d2a18190a865
      https://github.com/llvm/llvm-project/commit/764c1b7a4db1606438c8daea13c9d2a18190a865
  Author: Michael Collison <michael.collison at sifive.com>
  Date:   2020-09-25 (Fri, 25 Sep 2020)

  Changed paths:
    M llvm/include/llvm/Support/RISCVTargetParser.def
    M llvm/lib/Target/RISCV/RISCV.td
    A llvm/lib/Target/RISCV/RISCVSchedBullet.td

  Log Message:
  -----------
  [RISCV] Scheduler description for Bullet

Add the pipeline model for the RISC-V Bullet micro architecture.

Co-authored-by: Evandro Menezes <evandro.menezes at sifive.com>


  Commit: a000580a89718a1ff27a3129e34367b9a3fa1730
      https://github.com/llvm/llvm-project/commit/a000580a89718a1ff27a3129e34367b9a3fa1730
  Author: Evandro Menezes <ebahapo at users.noreply.github.com>
  Date:   2020-09-25 (Fri, 25 Sep 2020)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c

  Log Message:
  -----------
  [RISCV] Update driver tests

Add the RISC-V Bullet core to the driver tests.


Compare: https://github.com/llvm/llvm-project/compare/97702c3d9234...a000580a8971