[all-commits] [llvm/llvm-project] a88c72: [AArch64] PAC/BTI code generation for LLVM generat...

[Momchil Velikov via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a88c722e687e6780dcd6a58718350dc76fcc4cc9
      https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2020-09-25 (Fri, 25 Sep 2020)

  Changed paths:
    M clang/lib/CodeGen/CGDeclCXX.cpp
    M clang/lib/CodeGen/CodeGenModule.cpp
    M clang/lib/CodeGen/TargetInfo.cpp
    M clang/test/CodeGen/aarch64-branch-protection-attr.c
    M clang/test/CodeGen/aarch64-sign-return-address.c
    R clang/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
    M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
    M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
    M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
    M llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
    M llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
    M llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-2fixup-blr-terminator.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-outline-bti.ll
    M llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
    M llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
    M llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
    M llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
    M llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
    M llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
    M llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
    A llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-1.ll
    A llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
    A llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll
    M llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll

  Log Message:
  -----------
  [AArch64] PAC/BTI code generation for LLVM generated functions

PAC/BTI-related codegen in the AArch64 backend is controlled by a set
of LLVM IR function attributes, added to the function by Clang, based
on command-line options and GCC-style function attributes. However,
functions, generated in the LLVM middle end (for example,
asan.module.ctor or __llvm_gcov_write_out) do not get any attributes
and the backend incorrectly does not do any PAC/BTI code generation.

This patch record the default state of PAC/BTI codegen in a set of
LLVM IR module-level attributes, based on command-line options:

* "sign-return-address", with non-zero value means generate code to
  sign return addresses (PAC-RET), zero value means disable PAC-RET.

* "sign-return-address-all", with non-zero value means enable PAC-RET
  for all functions, zero value means enable PAC-RET only for
  functions, which spill LR.

* "sign-return-address-with-bkey", with non-zero value means use B-key
  for signing, zero value mean use A-key.

This set of attributes are always added for AArch64 targets (as
opposed, for example, to interpreting a missing attribute as having a
value 0) in order to be able to check for conflicts when combining
module attributed during LTO.

Module-level attributes are overridden by function level attributes.
All the decision making about whether to not to generate PAC and/or
BTI code is factored out into AArch64FunctionInfo, there shouldn't be
any places left, other than AArch64FunctionInfo, which directly
examine PAC/BTI attributes, except AArch64AsmPrinter.cpp, which
is/will-be handled by a separate patch.

Differential Revision: https://reviews.llvm.org/D85649