[all-commits] [llvm/llvm-project] 3ee87a: Precommit test updates

[Sanne Wouda via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ee87a976d52a2379d007046f9a1ad4a07f440c0
      https://github.com/llvm/llvm-project/commit/3ee87a976d52a2379d007046f9a1ad4a07f440c0
  Author: Sanne Wouda <Sanne.Wouda at arm.com>
  Date:   2020-09-17 (Thu, 17 Sep 2020)

  Changed paths:
    A llvm/test/CodeGen/AArch64/faddp-half.ll
    A llvm/test/CodeGen/AArch64/faddp.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

  Log Message:
  -----------
  Precommit test updates


  Commit: d5fd3d9b903ef6d96c6b3b82434dd0461faaba55
      https://github.com/llvm/llvm-project/commit/d5fd3d9b903ef6d96c6b3b82434dd0461faaba55
  Author: Sanne Wouda <Sanne.Wouda at arm.com>
  Date:   2020-09-17 (Thu, 17 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/faddp-half.ll
    M llvm/test/CodeGen/AArch64/faddp.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

  Log Message:
  -----------
  [AArch64] Match pairwise add/fadd pattern

D75689 turns the faddp pattern into a shuffle with vector add.

Match this new pattern in target-specific DAG combine, rather than ISel,
because legalization (for v2f32) turns it into a bit of a mess.

- extended to cover f16, f32, f64 and i64


Compare: https://github.com/llvm/llvm-project/compare/559f91981253...d5fd3d9b903e