[all-commits] [llvm/llvm-project] 65ef2e: [X86] Add test case for a masked load mask becomin...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 65ef2e50a29630f9f0fba4899045c0058dacfcb0
      https://github.com/llvm/llvm-project/commit/65ef2e50a29630f9f0fba4899045c0058dacfcb0
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-09-16 (Wed, 16 Sep 2020)

  Changed paths:
    M llvm/test/CodeGen/X86/masked_load.ll

  Log Message:
  -----------
  [X86] Add test case for a masked load mask becoming all ones after type legalization.

We should be able to turn this into a unmasked load. X86 has an
optimization to detect that the first and last element aren't masked
and then turn the whole thing into an unmasked load and a blend.
That transform is disabled on avx512 though.

But if we know the blend isn't needed, then the unmasked load by
itself should always be profitable.


  Commit: 89ee4c0314bd08143d954d80bf7678d3a3ecc15a
      https://github.com/llvm/llvm-project/commit/89ee4c0314bd08143d954d80bf7678d3a3ecc15a
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-09-16 (Wed, 16 Sep 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/masked_load.ll

  Log Message:
  -----------
  [DAGCombiner] Teach visitMLOAD to replace an all ones mask with an unmasked load

If we have an all ones mask, we can just a regular masked load. InstCombine already gets this in IR. But the all ones mask can appear after type legalization.

Only avx512 test cases are affected because X86 backend already looks for element 0 and the last element being 1. It replaces this with an unmasked load and blend. The all ones mask is a special case of that where the blend will be removed. That transform is only enabled on avx2 targets. I believe that's because a non-zero passthru on avx2 already requires a separate blend so its more profitable to handle mixed constant masks.

This patch adds a dedicated all ones handling to the target independent DAG combiner. I've skipped extending, expanding, and index loads for now. X86 doesn't use index so I don't know much about it. Extending made me nervous because I wasn't sure I could trust the memory VT had the right element count due to some weirdness in vector splitting. For expanding I wasn't sure if we needed different undef handling.

Differential Revision: https://reviews.llvm.org/D87788


Compare: https://github.com/llvm/llvm-project/compare/dee468622784...89ee4c0314bd