[all-commits] [llvm/llvm-project] 152c2b: [LegalizeTypes] Teach DAGTypeLegalizer::GenWidenVe...

[topperc via All-commits]

  Branch: refs/heads/release/11.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 152c2b1befb1879e690f228d95bbfe1bd381a1da
      https://github.com/llvm/llvm-project/commit/152c2b1befb1879e690f228d95bbfe1bd381a1da
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-07-27 (Mon, 27 Jul 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    A llvm/test/CodeGen/X86/pr46820.ll

  Log Message:
  -----------
  [LegalizeTypes] Teach DAGTypeLegalizer::GenWidenVectorLoads to pad with undef if needed when concatenating small or loads to match a larger load

In the included test case the align 16 allowed the v23f32 load to handled as load v16f32, load v4f32, and load v4f32(one element not used). These loads all need to be concatenated together into a final vector. In this case we tried to concatenate the two v4f32 loads to match the type of the v16f32 load so we could do a second concat_vectors, but those loads alone only add up to v8f32. So we need to two v4f32 undefs to pad it.

It appears we've tried to hack around a similar issue in this code before by adding undef padding to loads in one of the earlier loops in this function. Originally in r147964 by padding all loads narrower than previous loads to the same size. Later modifed to only the last load in r293088. This patch removes that earlier code and just handles it on demand where we know we need it.

Fixes PR46820

Differential Revision: https://reviews.llvm.org/D84463

(cherry picked from commit 8131e190647ac2b5b085b48a6e3b48c1d7520a66)