[all-commits] [llvm/llvm-project] 2d499d: [X86] Teach assembler parser to accept lsl and lar...

[topperc via All-commits]

  Branch: refs/heads/release/11.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 2d499d7912ac83ff7a943b9061a557c759176fe6
      https://github.com/llvm/llvm-project/commit/2d499d7912ac83ff7a943b9061a557c759176fe6
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-07-20 (Mon, 20 Jul 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrSystem.td
    M llvm/test/MC/X86/I286-64.s

  Log Message:
  -----------
  [X86] Teach assembler parser to accept lsl and lar with a 64 or 32 source register when the destination is a 64 register.

Previously we only accepted a 32-bit source with a 64-bit dest.

Accepting 64-bit as well is more consistent with gas behavior. I
think maybe we should accept 16 bit register as well, but I'm not
sure.

(cherry picked from commit 3c2a56a857227b6bc39285747269f02cd7a9dbe5)


  Commit: 40e2065d979b4417641105cff4a5ee9bbf67aebd
      https://github.com/llvm/llvm-project/commit/40e2065d979b4417641105cff4a5ee9bbf67aebd
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-07-20 (Mon, 20 Jul 2020)

  Changed paths:
    M llvm/lib/Target/X86/AsmParser/X86Operand.h
    M llvm/lib/Target/X86/X86InstrInfo.td
    M llvm/lib/Target/X86/X86InstrSystem.td
    M llvm/test/MC/X86/I286-32.s
    M llvm/test/MC/X86/I286-64.s
    M llvm/utils/TableGen/X86RecognizableInstr.cpp

  Log Message:
  -----------
  [X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register.

This matches GNU assembler behavior. Operand size is determined
only from the destination register.

(cherry picked from commit 71b49aa438b22b02230fff30e8874ff756336e6d)


Compare: https://github.com/llvm/llvm-project/compare/76c22b392f18...40e2065d979b