[all-commits] [llvm/llvm-project] d0b0b2: AMDGPU: Use IsSSA property check instead of assert...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d0b0b252e1e09f6203ca35ff87b58a2d4eafb8aa
      https://github.com/llvm/llvm-project/commit/d0b0b252e1e09f6203ca35ff87b58a2d4eafb8aa
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-06-29 (Mon, 29 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
    M llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
    M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir

  Log Message:
  -----------
  AMDGPU: Use IsSSA property check instead of asserting on isSSA

Also fix an SSA violation in a test the MIRParser/verifier fails to
catch. It's illegal to define a subregister in SSA. For the purpose of
the test, it just needs to define the super-register to use the
subregister in the use operand.