[all-commits] [llvm/llvm-project] 19ff00: [AArch64] Fix CollectLOH creating an AdrpAdd LOH w...

[AE via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 19ff00dab875d6184618c756df01b57acb908e82
      https://github.com/llvm/llvm-project/commit/19ff00dab875d6184618c756df01b57acb908e82
  Author: Amara Emerson <aemerson at apple.com>
  Date:   2020-06-01 (Mon, 01 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
    A llvm/test/CodeGen/AArch64/loh-use-between-adrp-add.mir

  Log Message:
  -----------
  [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg
between the two instructions.

If there's a pattern like:
$xA = ADRP foo @PAGE
[some killing use of reg Xb]
$Xb = ADDXri $Xa, 0, @PAGEOFF

CollectLOH would create an AdrpAdd LOH that resulted in the linker optimizing
this sequence into:
$xB = ADR foo
[some killing use of reg $Xb]
... and therefore clobbers the live $Xb register that was used by the
instruction in between.

This was discovered by a GlobalISel patch D78465 which broke up global variable
accesses into two pseudos, which in some cases could be moved apart.

Differential Revision: https://reviews.llvm.org/D80834


  Commit: f573d489b6fccca85e0f2b3765aa17a364a4b0a8
      https://github.com/llvm/llvm-project/commit/f573d489b6fccca85e0f2b3765aa17a364a4b0a8
  Author: Amara Emerson <aemerson at apple.com>
  Date:   2020-06-01 (Mon, 01 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/lib/Target/AArch64/AArch64InstrGISel.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AArch64/AArch64LegalizerInfo.h
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
    A llvm/test/CodeGen/AArch64/GlobalISel/legalize-global.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
    M llvm/test/CodeGen/AArch64/arm64-custom-call-saved-reg.ll
    M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
    M llvm/test/CodeGen/AArch64/dllimport.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize.

The concept of G_GLOBAL_VALUE is nice and simple, but always using it as the
representation for global var addressing until selection time creates some
problems in optimizing accesses in certain code/relocation models.

The problem comes from trying to optimize adrp -> add -> load/store sequences
in the most common "small" code model. These accesses can be optimized into an
adrp -> load with the add offset being folded into the load's immediate field.
If we try to keep all global var references as a single generic instruction
then by the time we get to the complex operand trying to match these, we end up
generating an adrp at the point of use. The real issue here is that we don't
have any form of CSE during selection, so the code size will bloat from many
redundant adrp's.

This patch custom legalizes small code mode non-GOT G_GLOBALs into target ADRP
and a new "target specific generic opcode" G_ADD_LOW. We also teach the
localizer to localize these instructions via the custom hook that was added
recently. Finally, the complex pattern for indexed loads/stores is extended to
try to fold these G_ADD_LOW instructions into the load immediate.

On -O0 CTMark, we see a 0.8% geomean code size improvement. We should also see
some minor performance improvements too.

Differential Revision: https://reviews.llvm.org/D78465


Compare: https://github.com/llvm/llvm-project/compare/776708b00bdd...f573d489b6fc