[all-commits] [llvm/llvm-project] a77208: PowerPC: Treat llvm.fma.f* intrinsic as using CTR ...

Tue May 12 15:07:48 PDT 2020

  Branch: refs/heads/a772082f
  Home:   https://github.com/llvm/llvm-project
  Commit: a772082fc1c7aa043175bb34a9363d3c119a7930
      https://github.com/llvm/llvm-project/commit/a772082fc1c7aa043175bb34a9363d3c119a7930
  Author: Justin Hibbits <jrh29 at alumni.cwru.edu>
  Date:   2020-05-12 (Tue, 12 May 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
    M llvm/test/CodeGen/PowerPC/spe.ll

  Log Message:
  -----------
  PowerPC: Treat llvm.fma.f* intrinsic as using CTR with SPE

Summary:
The SPE doesn't have a 'fma' instruction, so the intrinsic becomes a
libcall.  It really should become an expansion to two instructions, but
for some reason the compiler doesn't think that's as optimal as a
branch.  Since this lowering is done after CTR is allocated for loops,
tell the optimizer that CTR may be used in this case.  This prevents a
"Invalid PPC CTR loop!" assertion in the case that a fma() function call
is used in a C/C++ file, and clang converts it into an intrinsic.

Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D78668

  Commit: 95dcbfa0e5ce701ac20b34f1028a398996df3f34
      https://github.com/llvm/llvm-project/commit/95dcbfa0e5ce701ac20b34f1028a398996df3f34
  Author: Justin Hibbits <jrh29 at alumni.cwru.edu>
  Date:   2020-05-12 (Tue, 12 May 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    A llvm/test/CodeGen/PowerPC/spe-fastmath.ll

  Log Message:
  -----------
  PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE

Summary:
SPE doesn't have a fsel instruction, so don't try to lower to it.

This fixes a "Cannot select: tN: f64 = PPCISD::FSEL tX, tY, tZ" error.

Reviewed By: lkail
Differential Revision: https://reviews.llvm.org/D77773

  Commit: b901070f406129e71f9057357486ef8e1101ad6d
      https://github.com/llvm/llvm-project/commit/b901070f406129e71f9057357486ef8e1101ad6d
  Author: Justin Hibbits <chmeeedalf at gmail.com>
  Date:   2020-05-12 (Tue, 12 May 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h

  Log Message:
  -----------
  [PowerPC] Relax the restrictions on loading doubles with SPE

The original commit forced all 64-bit values to be loaded from indexed
registers, regardless of how close they were located to a given base
register.  This relaxes that, and permits some to be immediate-indexed
if they fit within a signed 255 (really 248, 8-byte aligned mask) byte
window.  Patch by kthomsen.

  Commit: 33e552d43617201799637faeabfdbe80e9d80a1b
      https://github.com/llvm/llvm-project/commit/33e552d43617201799637faeabfdbe80e9d80a1b
  Author: Justin Hibbits <chmeeedalf at gmail.com>
  Date:   2020-05-12 (Tue, 12 May 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp

  Log Message:
  -----------
  PowerPC: Fix SPE f64 VAARG handling.

SPE follows soft-float ABI for doubles, including VAARG passing.  For
soft-float, doubles are bitcast to i64, but for SPE they are not, so we
need to perform GPR alignment explicitly for SPE f64.

  Commit: df0a004bf3796a9a2b2d60b2c8f96e996aa36639
      https://github.com/llvm/llvm-project/commit/df0a004bf3796a9a2b2d60b2c8f96e996aa36639
  Author: Justin Hibbits <jrh29 at alumni.cwru.edu>
  Date:   2020-05-12 (Tue, 12 May 2020)

  Changed paths:
    M libunwind/include/__libunwind_config.h
    M libunwind/include/libunwind.h
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td

  Log Message:
  -----------
  PowerPCSPE: Stop libunwind from complaining about SPE registers

* Match SPE "DWARF" register numbers to GCC's instead of official DWARF
  documentation.
* Increase the register count to 148 from 112, even though the upper
  registers aren't saved (yet).

  Commit: 619fa4c9c852d438ec58bd7d4bedc9d1b8691a8f
      https://github.com/llvm/llvm-project/commit/619fa4c9c852d438ec58bd7d4bedc9d1b8691a8f
  Author: Justin Hibbits <jrh29 at alumni.cwru.edu>
  Date:   2020-05-12 (Tue, 12 May 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp

  Log Message:
  -----------
  PowerPC: Don't hoist float multiply + add to fused operation on SPE

SPE doesn't have a fmadd instruction, so don't bother hoisting a
multiply and add sequence to this, as it'd become just a library call.
Hoisting happens too late for the CTR usability test to veto using the
CTR in a loop, and results in an assert "Invalid PPC CTR loop!".

  Commit: bd718572089afe9f4eb627ec153a2b33d781935f
      https://github.com/llvm/llvm-project/commit/bd718572089afe9f4eb627ec153a2b33d781935f
  Author: Justin Hibbits <jrh29 at alumni.cwru.edu>
  Date:   2020-05-12 (Tue, 12 May 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCInstrSPE.td
    M llvm/test/CodeGen/PowerPC/spe.ll

  Log Message:
  -----------
  PowerPC: Fix SPE extloadf32 handling.

The patterns were incorrect copies from the FPU code, and are
unnecessary, since there's no extended load for SPE.  Just let LLVM
itself do the work by marking it expand.

  Commit: e82f0d991fc01a8e509f4d6c2f5139af2d29f913
      https://github.com/llvm/llvm-project/commit/e82f0d991fc01a8e509f4d6c2f5139af2d29f913
  Author: Justin Hibbits <jrh29 at alumni.cwru.edu>
  Date:   2020-05-12 (Tue, 12 May 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
    A llvm/test/CodeGen/PowerPC/spe-spills.ll

  Log Message:
  -----------
  PowerPC: Add emergency stack spill slots for SPE

The powerpcspe 64-bit load/store only allows a 8-bit delta (32 64-bit
words), so if the stack size is any larger than that, we need extra
spill slots for doing indexing.

Compare: https://github.com/llvm/llvm-project/compare/a772082fc1c7%5E...e82f0d991fc0