[all-commits] [llvm/llvm-project] 8c71c2: [X86] getShuffleScalarElt - consistently use SDVal...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8c71c2291e81b1348fdedbda7e7600c5c2eeed7c
      https://github.com/llvm/llvm-project/commit/8c71c2291e81b1348fdedbda7e7600c5c2eeed7c
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-05-06 (Wed, 06 May 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp

  Log Message:
  -----------
  [X86] getShuffleScalarElt - consistently use SDValue. NFC.

We never need to call this from anything but ISD::SHUFFLE_VECTOR or target shuffles so shouldn't need to address SDNode directly.


  Commit: 8817334ce3c71bf4c087adde60e11c7fe0aaceba
      https://github.com/llvm/llvm-project/commit/8817334ce3c71bf4c087adde60e11c7fe0aaceba
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-05-06 (Wed, 06 May 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
    M llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll

  Log Message:
  -----------
  [X86] getShuffleScalarElt - add CONCAT_VECTORS/INSERT_VECTOR_ELT support.

This helped fix some i686 vXi64 broadcast folds that were becoming v2Xi32 broadcasts because we didn't match the broadcast until after SimplifyDemandedBits worked out we only used the bottom 32-bits in PMUL(U)DQ and type legalization had split the original i64 load.

A couple of regressions occurred which required some fixups - adding concat_vectors(broadcast_load,broadcast_load) splat support and recognising (unnecessary) unary shuffles of already broadcasted vectors.

This came about as part of the work investigating vector load combining from shuffles for PR42550.


Compare: https://github.com/llvm/llvm-project/compare/2058c98715f6...8817334ce3c7