[all-commits] [llvm/llvm-project] 5d1061: [mlir][StandardToSPIRV] Emulate bitwidths not supp...

[Han-Chung Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d10613b6edcfb1e50cf08c7ec97ed872d0989be
      https://github.com/llvm/llvm-project/commit/5d10613b6edcfb1e50cf08c7ec97ed872d0989be
  Author: Hanhan Wang <hanchung at google.com>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
    M mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir

  Log Message:
  -----------
  [mlir][StandardToSPIRV] Emulate bitwidths not supported for store op.

Summary:
As D78974, this patch implements the emulation for store op. The emulation is
done with atomic operations. E.g., if the storing value is i8, rewrite the
StoreOp to:

 1) load a 32-bit integer
 2) clear 8 bits in the loading value
 3) store 32-bit value back
 4) load a 32-bit integer
 5) modify 8 bits in the loading value
 6) store 32-bit value back

The step 1 to step 3 are done by AtomicAnd as one atomic step, and the step 4
to step 6 are done by AtomicOr as another atomic step.

Differential Revision: https://reviews.llvm.org/D79272