[all-commits] [llvm/llvm-project] 2a0722: [SelectionDAG] Add an assert that the input VT and...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2a07221cf3029f2b55503e1c3847699eb6090ad6
      https://github.com/llvm/llvm-project/commit/2a07221cf3029f2b55503e1c3847699eb6090ad6
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2020-03-30 (Mon, 30 Mar 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  Log Message:
  -----------
  [SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are the same.

Differential Revision: https://reviews.llvm.org/D77092