[all-commits] [llvm/llvm-project] 37b9cc: [ARM] Sink splats to vector float instructions

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 37b9cc8f29e993ba9894402dd87f9c4be83cb8f6
      https://github.com/llvm/llvm-project/commit/37b9cc8f29e993ba9894402dd87f9c4be83cb8f6
  Author: David Green <david.green at arm.com>
  Date:   2020-03-26 (Thu, 26 Mar 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll

  Log Message:
  -----------
  [ARM] Sink splats to vector float instructions

Some MVE floating point instructions have gpr register variants that take
the scalar gpr value and splat them to all lanes. In order to accept
them in loops, the shuffle_vector and insert need to be sunk down into
the loop, next to the instruction so that ISel can see the whole
pattern.

This does that sinking for FAdd, FSub, FMul and FCmp. The patterns for
mul are slightly more constrained as there are no fms variants taking
register arguments.

Differential Revision: https://reviews.llvm.org/D76023