[all-commits] [llvm/llvm-project] 68224c: [TargetLowering] Only demand a rotation's modulo a...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 68224c19522220aa27bb0aee9e0f906c0d71f4f9
      https://github.com/llvm/llvm-project/commit/68224c19522220aa27bb0aee9e0f906c0d71f4f9
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AVR/AVRISelLowering.cpp
    M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
    M llvm/test/CodeGen/PowerPC/rotl-2.ll
    M llvm/test/CodeGen/SystemZ/rot-01.ll
    M llvm/test/CodeGen/SystemZ/rot-02.ll
    M llvm/test/CodeGen/SystemZ/shift-04.ll
    M llvm/test/CodeGen/SystemZ/shift-08.ll
    M llvm/test/CodeGen/Thumb2/thumb2-ror.ll
    M llvm/test/CodeGen/X86/combine-rotates.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-512.ll

  Log Message:
  -----------
  [TargetLowering] Only demand a rotation's modulo amount bits

ISD::ROTL/ROTR rotation values are guaranteed to act as a modulo amount, so for power-of-2 bitwidths we only need the lowest bits.

Differential Revision: https://reviews.llvm.org/D76201