[all-commits] [llvm/llvm-project] 5c6b1a: [TableGen] Fix spurious type error in bit assignment.

[Simon Tatham via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5c6b1a6dfdb428a347a25527a4aebba72cd42a3a
      https://github.com/llvm/llvm-project/commit/5c6b1a6dfdb428a347a25527a4aebba72cd42a3a
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2020-02-07 (Fri, 07 Feb 2020)

  Changed paths:
    M llvm/lib/TableGen/TGParser.cpp
    M llvm/test/TableGen/BitsInit.td

  Log Message:
  -----------
  [TableGen] Fix spurious type error in bit assignment.

Summary:
The following example gives the error message "expected value of type
'bits<32>', got 'bit'" on the assignment.

    class Instruction { bits<32> encoding; }
    def foo: Instruction { let encoding{10} = !eq(0, 1); }

But there's nothing wrong with this code: 'bit' is a perfectly good
type for the RHS of an assignment to a //single bit// of an
instruction encoding.

The problem is that `ParseBodyItem` is accidentally type-checking the
RHS against the full type of the `encoding` field, without adjusting
it in the case where we're only assigning to a subset of the bits. The
fix is trivial.

Reviewers: nhaehnle, hfinkel

Reviewed By: hfinkel

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74220