[all-commits] [llvm/llvm-project] abe6d1: [mlir] Emit a fatal error when the assembly format...

[River Riddle via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: abe6d1174df422915958c49c0367471c2de5df7a
      https://github.com/llvm/llvm-project/commit/abe6d1174df422915958c49c0367471c2de5df7a
  Author: River Riddle <riddleriver at gmail.com>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M mlir/test/mlir-tblgen/op-format-spec.td
    M mlir/tools/mlir-tblgen/OpFormatGen.cpp

  Log Message:
  -----------
  [mlir] Emit a fatal error when the assembly format is invalid

This revision makes sure that errors emitted outside of testing are treated as fatal errors. This avoids the current silent failures that occur when the format is invalid.