[all-commits] [llvm/llvm-project] 4fdae2: AMDGPU/GlobalISel: Add selection tests for G_ATOMI...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 4fdae24733d223b773f2bd48081e5e147739afa5
      https://github.com/llvm/llvm-project/commit/4fdae24733d223b773f2bd48081e5e147739afa5
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-24 (Fri, 24 Jan 2020)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Add selection tests for G_ATOMICRMW_ADD


  Commit: 84e035d8f1d635d202692e3c38c9c96aa1e08088
      https://github.com/llvm/llvm-project/commit/84e035d8f1d635d202692e3c38c9c96aa1e08088
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-24 (Fri, 24 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

  Log Message:
  -----------
  AMDGPU: Don't check constant address space for atomic stores

We define a separate list for storable address spaces. This saves
entry in the matcher table address space list.


  Commit: d8328c0b6240234c8036f16c081ab7e8dc98cce8
      https://github.com/llvm/llvm-project/commit/d8328c0b6240234c8036f16c081ab7e8dc98cce8
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-24 (Fri, 24 Jan 2020)

  Changed paths:
    M llvm/utils/TableGen/CodeGenRegisters.cpp

  Log Message:
  -----------
  TableGen: Work around assert on Mips register definitions

This would hit the "Biggest class wasn't first" assert in
getMatchingSubClassWithSubRegs in a future patch for EXTRACT_SUBREG
handling.

Mips defines 4 identical register classes (MSA128B, MSA128H, MSA128BW,
MSA128D). These have the same set of registers, and only differ by the
isel type. I believe this is an ill formed way of defining registers,
that probably is just to work around the inconvenience of mixing
different types in a single register class in DAG patterns.

Since these all have the same size, they would all sort to the
beginning, but you would not necessarily get the same super register
at the front as the assert enforces. Breaking the ambiguity by also
sorting by name doesn't work, since each of these register classes all
want to be first. Force sorting of the original register class if the
size is the same.


  Commit: 9c346464c15c9f42fd641c33ca4c35b31556a661
      https://github.com/llvm/llvm-project/commit/9c346464c15c9f42fd641c33ca4c35b31556a661
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-24 (Fri, 24 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
    M llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
    M llvm/test/CodeGen/X86/GlobalISel/shl-scalar-widening.ll
    M llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
    M llvm/test/TableGen/GlobalISelEmitterSubreg.td
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG

This previously only handled EXTRACT_SUBREGs from leafs, such as
operands directly in the original output. Handle extracting from a
result instruction.


Compare: https://github.com/llvm/llvm-project/compare/a107f8641763...9c346464c15c