[all-commits] [llvm/llvm-project] 8615ee: AMDGPU: Partially merge indirect register write ha...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8615eeb455618fabe962f6951ccd8fe95b26bb15
      https://github.com/llvm/llvm-project/commit/8615eeb455618fabe962f6951ccd8fe95b26bb15
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-20 (Mon, 20 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td

  Log Message:
  -----------
  AMDGPU: Partially merge indirect register write handling

a785209bc2fb switched to using a pseudos instead of manually tying
operands on the regular instruction. The VGPR indexing mode path
should have the same problems that change attempted to avoid, so these
should use the same strategy.

Use a single pseudo for the VGPR indexing mode and movreld paths, and
expand it based on the subtarget later. These have essentially the
same constraints, reading the index from m0.

Switch from using an offset to the subregister index directly, instead
of computing an offset and re-adding it back. Also add missing pseudos
for existing register class sizes.


  Commit: 9b13b4a0e3a192a3b0d938bfaa71ce6dc0740ece
      https://github.com/llvm/llvm-project/commit/9b13b4a0e3a192a3b0d938bfaa71ce6dc0740ece
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-20 (Mon, 20 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir

  Log Message:
  -----------
  AMDGPU: Prepare to use scalar register indexing

Define pseudos mirroring the the VGPR indexing ones, and adjust the
operands in the s_movrel* instructions to avoid the result def.


Compare: https://github.com/llvm/llvm-project/compare/c12a5917d2f2...9b13b4a0e3a1