[all-commits] [llvm/llvm-project] c05a11: [SelectionDAG] ComputeKnownBits - merge getValidMi...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c05a11108b9a9deb266c3c1758677462df61e05e
      https://github.com/llvm/llvm-project/commit/c05a11108b9a9deb266c3c1758677462df61e05e
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-01-14 (Tue, 14 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/combine-shl.ll

  Log Message:
  -----------
  [SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SHL handling.

As mentioned by @nikic on rGef5debac4302, we can merge the guaranteed bottom zero bits from the shifted value, and then, if a min shift amount is known, zero out the bottom bits as well.