[all-commits] [llvm/llvm-project] 65678d: [mlir][VectorOps] Implement strided_slice conversion

[Nicolas Vasilache via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 65678d938431c90408afa8d255cbed3d8ed8273f
      https://github.com/llvm/llvm-project/commit/65678d938431c90408afa8d255cbed3d8ed8273f
  Author: Nicolas Vasilache <ntv at google.com>
  Date:   2020-01-09 (Thu, 09 Jan 2020)

  Changed paths:
    M mlir/include/mlir/IR/Attributes.h
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir

  Log Message:
  -----------
  [mlir][VectorOps] Implement strided_slice conversion

Summary:
This diff implements the progressive lowering of strided_slice to either:
  1. extractelement + insertelement for the 1-D case
  2. extract + optional strided_slice + insert for the n-D case.

This combines properly with the other conversion patterns to lower all the way to LLVM.

Appropriate tests are added.

Reviewers: ftynse, rriddle, AlexEichenberger, andydavis1, tetuante

Reviewed By: andydavis1

Subscribers: merge_guards_bot, mehdi_amini, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72310