[all-commits] [llvm/llvm-project] 68e70f: AMDGPU: Fix not using v_cvt_f16_[iu]16

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 68e70fb098a27d08e6dd039995c2acf14b894abc
      https://github.com/llvm/llvm-project/commit/68e70fb098a27d08e6dd039995c2acf14b894abc
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-07 (Tue, 07 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
    M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
    M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll

  Log Message:
  -----------
  AMDGPU: Fix not using v_cvt_f16_[iu]16

We weren't treating i16->f16 casts as legal on targets with these
instructions, and always using a pair of casts through i32.


  Commit: bd8d696c145edba207f7240407ac092b02b68300
      https://github.com/llvm/llvm-project/commit/bd8d696c145edba207f7240407ac092b02b68300
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-07 (Tue, 07 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

  Log Message:
  -----------
  AMDGPU: Use ImmLeaf


  Commit: de46ab698bd6a174e33e90207342f2ecece05a06
      https://github.com/llvm/llvm-project/commit/de46ab698bd6a174e33e90207342f2ecece05a06
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-07 (Tue, 07 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td

  Log Message:
  -----------
  AMDGPU: Fix misleading, misplaced end block comments


  Commit: c3a10faadc12614b0e664163115858d214b90af6
      https://github.com/llvm/llvm-project/commit/c3a10faadc12614b0e664163115858d214b90af6
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-07 (Tue, 07 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/VOPCInstructions.td

  Log Message:
  -----------
  AMDGPU: Remove VOP3Mods0Clamp0OMod

Now that overridable default operands work, there's no reason to use
complex patterns to just produce 0s.


  Commit: 449ab1050977e0a5a1757552f13ca1329a7238f5
      https://github.com/llvm/llvm-project/commit/449ab1050977e0a5a1757552f13ca1329a7238f5
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-07 (Tue, 07 Jan 2020)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll

  Log Message:
  -----------
  AMDGPU: Add baseline test for missing pattern

The optimization to turn an add into a sub isn't triggering when the
pattern to use the zeroed high bits is used.


Compare: https://github.com/llvm/llvm-project/compare/640d0ba87600...449ab1050977