[all-commits] [llvm/llvm-project] cdd25a: [DebugInfo][SelectionDAG] Change order while trans...

[chbessonova via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: cdd25a4c7410d9af69df4ebe0e640506b8e977b4
      https://github.com/llvm/llvm-project/commit/cdd25a4c7410d9af69df4ebe0e640506b8e977b4
  Author: Kristina Bessonova <kbessonova at accesssoftek.com>
  Date:   2019-12-26 (Thu, 26 Dec 2019)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    A llvm/test/DebugInfo/X86/sdag-transfer-dbgvalue.ll

  Log Message:
  -----------
  [DebugInfo][SelectionDAG] Change order while transferring SDDbgValue to another node

SelectionDAG::transferDbgValues() can 'reattach' SDDbgValue from one to
another node, but doesn't change its source order. If the destination node has
the order greater than the SDDbgValue, there are two possible issues
revealed later:

* If debug info is attached to an instruction that is the first definition
of a register, this ends up with a def-after-use and the debug info
gets 'undef' later.

* If MIR has another definition of a register above the debug info,
the debug info may represent a source variable incorrectly because
it appears (significantly) before an instruction corresponded
to this debug info.

So, the patch changes the order of an SDDbgValue when it is moved
to a node with greater order.

Reviewers: dblaikie, jmorse, aprantl

Reviewed By: aprantl

Subscribers: aprantl, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71175