[all-commits] [llvm/llvm-project] d688a6: AMDGPU/GlobalISel: Simplify code

Matt Arsenault via All-commits all-commits at lists.llvm.org
Sat Dec 21 01:55:43 PST 2019


  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d688a6739df527d14dfe578d8bc97439d3884a73
      https://github.com/llvm/llvm-project/commit/d688a6739df527d14dfe578d8bc97439d3884a73
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2019-12-21 (Sat, 21 Dec 2019)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

  Log Message:
  -----------
  AMDGPU/GlobalISel: Simplify code

This can directly access the register bank, and doesn't need to get it
through the ID.


  Commit: dff3f8d74240144c35e78978a73646aa34faf400
      https://github.com/llvm/llvm-project/commit/dff3f8d74240144c35e78978a73646aa34faf400
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2019-12-21 (Sat, 21 Dec 2019)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix missing scc imp-def on scalar and/or/xor


  Commit: 42a26445f9e68d55bcc4b8d1b4ced83a56d7743c
      https://github.com/llvm/llvm-project/commit/42a26445f9e68d55bcc4b8d1b4ced83a56d7743c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2019-12-21 (Sat, 21 Dec 2019)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix misuse of div_scale intrinsics

Confusingly, the intrinsic operands do not match the
instruction/custom node. The order is shuffled, and the 3rd operand is
an immediate to select operands.

I'm not 100% sure I did this right, but fdiv still doesn't select end
to end and it will be easier to tell when it does. This at least
avoids an assertion in RegBankSelect and allows hitting the fallback
on selection.


Compare: https://github.com/llvm/llvm-project/compare/7ece0ee3dd7c...42a26445f9e6


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