[all-commits] [llvm/llvm-project] ce3d1c: [libunwind][RISCV] Add 64-bit RISC-V support

[Sam Elliott via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ce3d1c6d61dcd96f44492516f8b613bbcadaeb8e
      https://github.com/llvm/llvm-project/commit/ce3d1c6d61dcd96f44492516f8b613bbcadaeb8e
  Author: Sam Elliott <selliott at lowrisc.org>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M libunwind/include/__libunwind_config.h
    M libunwind/include/libunwind.h
    M libunwind/src/Registers.hpp
    M libunwind/src/UnwindCursor.hpp
    M libunwind/src/UnwindRegistersRestore.S
    M libunwind/src/UnwindRegistersSave.S
    M libunwind/src/config.h
    M libunwind/src/libunwind.cpp

  Log Message:
  -----------
  [libunwind][RISCV] Add 64-bit RISC-V support

Summary:
Add unwinding support for 64-bit RISC-V.

This is from the FreeBSD implementation with the following minor
changes:

- Renamed and renumbered DWARF registers to match the RISC-V ABI [1]
- Use the ABI mneumonics in getRegisterName() instead of the exact
   register names
- Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit
   ABI in the future.

[1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

Patch by Mitchell Horne (mhorne)

Reviewers: lenary, luismarques, compnerd, phosek

Reviewed By: lenary, luismarques

Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski, simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl, benna, lenary, s.egerton, luismarques, emaste, cfe-commits

Differential Revision: https://reviews.llvm.org/D68362