[all-commits] [llvm/llvm-project] d9bb70: [NFC] Change SelectionDAG::getMemBasePlusOffset() ...

Fri Dec 13 13:40:53 PST 2019

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d9bb70acd7f6da7c4637826d5ae942ae61bf9494
      https://github.com/llvm/llvm-project/commit/d9bb70acd7f6da7c4637826d5ae942ae61bf9494
  Author: Alex Richardson <Alexander.Richardson at cl.cam.ac.uk>
  Date:   2019-12-13 (Fri, 13 Dec 2019)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  Log Message:
  -----------
  [NFC] Change SelectionDAG::getMemBasePlusOffset() to use int64_t

Summary:
This change is preparatory work to use this helper functions in more places.
Currently the function only allows positive offsets, but there are cases
where we want to subtract an offset from an existing pointer.

The motivation for this change is our out-of-tree CHERI backend
(https://github.com/CTSRD-CHERI/llvm-project). We use a separate register
type to store pointers (128-bit capabilities, which are effectively
unforgeable and monotonic fat pointers). These capabilities permit a
reduced set of operations and therefore use a separate ValueType (iFATPTR).
to represent pointers implemented as capabilities.
Therefore, we need to avoid using ISD::ADD for our patterns that operate
on pointers and need to use a function that chooses ISD::ADD or a new
ISD::PTRADD opcode depending on the value type.

We originally added a new DAG.getPointerAdd() function, but after this
patch series we can modify the implementation of getMemBasePlusOffset()
instead. Avoiding direct uses of ISD::ADD for pointer types will
significantly reduce the amount of assertion/instruction selection
failures for us in future upstream merges.

Reviewers: spatel

Reviewed By: spatel

Subscribers: merge_guards_bot, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71204

  Commit: ea8888d1af3a992d82d1ff3bf99537220828d388
      https://github.com/llvm/llvm-project/commit/ea8888d1af3a992d82d1ff3bf99537220828d388
  Author: Alex Richardson <Alexander.Richardson at cl.cam.ac.uk>
  Date:   2019-12-13 (Fri, 13 Dec 2019)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  Log Message:
  -----------
  [NFC] Add a SDValue overload for SelectionDAG::getMemBasePlusOffset()

Summary:
This change is preparatory work to use this helper functions in more places.
Currently the function only allows integer constants offsets, but there
are cases where we can use an existing SDValue parameter.

The motivation for this change is our out-of-tree CHERI backend
(https://github.com/CTSRD-CHERI/llvm-project). We use a separate register
type to store pointers (128-bit capabilities, which are effectively
unforgeable and monotonic fat pointers). These capabilities permit a
reduced set of operations and therefore use a separate ValueType (iFATPTR).
to represent pointers implemented as capabilities.
Therefore, we need to avoid using ISD::ADD for our patterns that operate
on pointers and need to use a function that chooses ISD::ADD or a new
ISD::PTRADD opcode depending on the value type.

We originally added a new DAG.getPointerAdd() function, but after this
patch series we can modify the implementation of getMemBasePlusOffset()
instead. Avoiding direct uses of ISD::ADD for pointer types will
significantly reduce the amount of assertion/instruction selection
failures for us in future upstream merges.

Reviewers: spatel, craig.topper

Reviewed By: spatel, craig.topper

Subscribers: craig.topper, merge_guards_bot, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71205

  Commit: fc83f53a86d802fc2d56aac4eb3dc53998751042
      https://github.com/llvm/llvm-project/commit/fc83f53a86d802fc2d56aac4eb3dc53998751042
  Author: Alex Richardson <Alexander.Richardson at cl.cam.ac.uk>
  Date:   2019-12-13 (Fri, 13 Dec 2019)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  Log Message:
  -----------
  [NFC] Implement SelectionDAG::getObjectPtrOffset() using getMemBasePlusOffset()

Summary:
This change is preparatory work to use this helper functions in more places.
In order to make this change, getMemBasePlusOffset() has been extended to
also take a SDNodeFlags parameter.

The motivation for this change is our out-of-tree CHERI backend
(https://github.com/CTSRD-CHERI/llvm-project). We use a separate register
type to store pointers (128-bit capabilities, which are effectively
unforgeable and monotonic fat pointers). These capabilities permit a
reduced set of operations and therefore use a separate ValueType (iFATPTR).
to represent pointers implemented as capabilities.
Therefore, we need to avoid using ISD::ADD for our patterns that operate
on pointers and need to use a function that chooses ISD::ADD or a new
ISD::PTRADD opcode depending on the value type.

We originally added a new DAG.getPointerAdd() function, but after this
patch series we can modify the implementation of getMemBasePlusOffset()
instead. Avoiding direct uses of ISD::ADD for pointer types will
significantly reduce the amount of assertion/instruction selection
failures for us in future upstream merges.

Reviewers: spatel

Reviewed By: spatel

Subscribers: merge_guards_bot, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71206

  Commit: 11448eeb72e1392f9f4ad072866c2c6dc82d14bc
      https://github.com/llvm/llvm-project/commit/11448eeb72e1392f9f4ad072866c2c6dc82d14bc
  Author: Alex Richardson <Alexander.Richardson at cl.cam.ac.uk>
  Date:   2019-12-13 (Fri, 13 Dec 2019)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

  Log Message:
  -----------
  [NFC] Use SelectionDAG::getMemBasePlusOffset() instead of getNode(ISD::ADD)

Summary:
To find potential opportunities to use getMemBasePlusOffset() I looked at
all ISD::ADD uses found with the regex getNode\(ISD::ADD,.+,.+Ptr
in lib/CodeGen/SelectionDAG. If this patch is accepted I will convert
the files in the individual backends too.

The motivation for this change is our out-of-tree CHERI backend
(https://github.com/CTSRD-CHERI/llvm-project). We use a separate register
type to store pointers (128-bit capabilities, which are effectively
unforgeable and monotonic fat pointers). These capabilities permit a
reduced set of operations and therefore use a separate ValueType (iFATPTR).
to represent pointers implemented as capabilities.
Therefore, we need to avoid using ISD::ADD for our patterns that operate
on pointers and need to use a function that chooses ISD::ADD or a new
ISD::PTRADD opcode depending on the value type.

We originally added a new DAG.getPointerAdd() function, but after this
patch series we can modify the implementation of getMemBasePlusOffset()
instead. Avoiding direct uses of ISD::ADD for pointer types will
significantly reduce the amount of assertion/instruction selection
failures for us in future upstream merges.

Reviewers: spatel

Reviewed By: spatel

Subscribers: merge_guards_bot, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71207

  Commit: 9cb7a1be2a430a50fb5644b3f48d4a1544034fb9
      https://github.com/llvm/llvm-project/commit/9cb7a1be2a430a50fb5644b3f48d4a1544034fb9
  Author: Alex Richardson <Alexander.Richardson at cl.cam.ac.uk>
  Date:   2019-12-13 (Fri, 13 Dec 2019)

  Changed paths:
    M compiler-rt/test/lsan/TestCases/Linux/guard-page.c

  Log Message:
  -----------
  [LSAN] Increase stack space for guard-page.c test

Summary:
When running the tests on a Ubuntu 18.04 machine this test is crashing for
me inside the runtime linker. My guess is that it is trying to save more
registers (possibly large vector ones) and the current stack space is not
sufficient.

Reviewers: samsonov, kcc, eugenis

Reviewed By: eugenis

Subscribers: eugenis, merge_guards_bot, #sanitizers, llvm-commits

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D71461

Compare: https://github.com/llvm/llvm-project/compare/dd8a7fcdd73d...9cb7a1be2a43