[all-commits] [llvm/llvm-project] 5d9869: [IR] Split out target specific intrinsic enums int...

[Reid Kleckner via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d986953c8b917bacfaa1f800fc1e242559f76be
      https://github.com/llvm/llvm-project/commit/5d986953c8b917bacfaa1f800fc1e242559f76be
  Author: Reid Kleckner <rnk at google.com>
  Date:   2019-12-11 (Wed, 11 Dec 2019)

  Changed paths:
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/CodeGen/CGException.cpp
    M clang/lib/CodeGen/CGExprScalar.cpp
    M clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
    M llvm/include/llvm/Analysis/TargetTransformInfo.h
    M llvm/include/llvm/Analysis/VectorUtils.h
    M llvm/include/llvm/IR/CMakeLists.txt
    M llvm/include/llvm/IR/CallSite.h
    M llvm/include/llvm/IR/Function.h
    M llvm/include/llvm/IR/GlobalValue.h
    M llvm/include/llvm/IR/InstrTypes.h
    M llvm/include/llvm/IR/Intrinsics.h
    M llvm/lib/Analysis/ConstantFolding.cpp
    M llvm/lib/Analysis/MemoryLocation.cpp
    M llvm/lib/Analysis/ValueTracking.cpp
    M llvm/lib/CodeGen/CodeGenPrepare.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    M llvm/lib/CodeGen/TypePromotion.cpp
    M llvm/lib/CodeGen/WasmEHPrepare.cpp
    M llvm/lib/IR/AutoUpgrade.cpp
    M llvm/lib/IR/Function.cpp
    M llvm/lib/IR/Verifier.cpp
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
    M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
    M llvm/lib/Target/ARM/ARMParallelDSP.cpp
    M llvm/lib/Target/ARM/MVETailPredication.cpp
    M llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
    M llvm/lib/Target/Hexagon/HexagonGenExtract.cpp
    M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
    M llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
    M llvm/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp
    M llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
    M llvm/lib/Target/Mips/MipsInstructionSelector.cpp
    M llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
    M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
    M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
    M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
    M llvm/lib/Target/NVPTX/NVVMIntrRange.cpp
    M llvm/lib/Target/NVPTX/NVVMReflect.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZTDC.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/lib/Target/X86/X86FastISel.cpp
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/lib/Target/X86/X86InstructionSelector.cpp
    M llvm/lib/Target/X86/X86IntrinsicsInfo.h
    M llvm/lib/Target/X86/X86WinEHState.cpp
    M llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
    M llvm/lib/Target/XCore/XCoreISelLowering.cpp
    M llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
    M llvm/test/TableGen/intrinsic-long-name.td
    M llvm/test/TableGen/intrinsic-struct.td
    M llvm/unittests/IR/IRBuilderTest.cpp
    M llvm/utils/TableGen/IntrinsicEmitter.cpp

  Log Message:
  -----------
  [IR] Split out target specific intrinsic enums into separate headers

This has two main effects:
- Optimizes debug info size by saving 221.86 MB of obj file size in a
  Windows optimized+debug build of 'all'. This is 3.03% of 7,332.7MB of
  object file size.
- Incremental step towards decoupling target intrinsics.

The enums are still compact, so adding and removing a single
target-specific intrinsic will trigger a rebuild of all of LLVM.
Assigning distinct target id spaces is potential future work.

Part of PR34259

Reviewers: efriedma, echristo, MaskRay

Reviewed By: echristo, MaskRay

Differential Revision: https://reviews.llvm.org/D71320