[all-commits] [llvm/llvm-project] 411bfe: [ARM] Add and update a lot of VLDn tests. NFC

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 411bfe476b758c09a0c9d4b3176e46f0a70de3bb
      https://github.com/llvm/llvm-project/commit/411bfe476b758c09a0c9d4b3176e46f0a70de3bb
  Author: David Green <david.green at arm.com>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    A llvm/test/CodeGen/Thumb2/mve-vld2.ll
    A llvm/test/CodeGen/Thumb2/mve-vld3.ll
    A llvm/test/CodeGen/Thumb2/mve-vld4.ll
    A llvm/test/CodeGen/Thumb2/mve-vst2.ll
    A llvm/test/CodeGen/Thumb2/mve-vst3.ll
    A llvm/test/CodeGen/Thumb2/mve-vst4.ll
    M llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll

  Log Message:
  -----------
  [ARM] Add and update a lot of VLDn tests. NFC


  Commit: 882f23caeae5ad3ec1806eb6ec387e3611649d54
      https://github.com/llvm/llvm-project/commit/882f23caeae5ad3ec1806eb6ec387e3611649d54
  Author: David Green <david.green at arm.com>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
    M llvm/test/CodeGen/Thumb2/mve-vld2.ll
    M llvm/test/CodeGen/Thumb2/mve-vld4.ll
    M llvm/test/CodeGen/Thumb2/mve-vst2.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4.ll
    M llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll

  Log Message:
  -----------
  [ARM] MVE interleaving load and stores.

Now that we have the intrinsics, we can add VLD2/4 and VST2/4 lowering
for MVE. This works the same way as Neon, recognising the load/shuffles
combination and converting them into intrinsics in a pre-isel pass,
which just calls getMaxSupportedInterleaveFactor, lowerInterleavedLoad
and lowerInterleavedStore.

The main difference to Neon is that we do not have a VLD3 instruction.
Otherwise most of the code works very similarly, with just some minor
differences in the form of the intrinsics to work around. VLD3 is
disabled by making isLegalInterleavedAccessType return false for those
cases.

We may need some other future adjustments, such as VLD4 take up half the
available registers so should maybe cost more. This patch should get the
basics in though.

Differential Revision: https://reviews.llvm.org/D69392


Compare: https://github.com/llvm/llvm-project/compare/b91f798fde42...882f23caeae5