[all-commits] [llvm/llvm-project] 5b9e4d: [ARM, MVE] Use VMOV.{S8, S16} for sign-extended extr...

[Simon Tatham via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5b9e4daef06dcfefc786737a32c8bbb5bd0fc5c4
      https://github.com/llvm/llvm-project/commit/5b9e4daef06dcfefc786737a32c8bbb5bd0fc5c4
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2019-11-13 (Wed, 13 Nov 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    A llvm/test/CodeGen/Thumb2/mve-extractelt.ll

  Log Message:
  -----------
  [ARM,MVE] Use VMOV.{S8,S16} for sign-extended extractelement.

MVE includes instructions that extract an 8- or 16-bit lane from a
vector and sign-extend it into the output 32-bit GPR. `ARMInstrMVE.td`
already included isel patterns to select those instructions in
response to the `ARMISD::VGETLANEs` selection-DAG node type. But
`ARMISD::VGETLANEs` was never actually generated, because the code
that creates it was conditioned on NEON only.

It's an easy fix to enable the same code for integer MVE, and now IR
that sign-extends the result of an extractelement (whether explicitly
or as part of the function call ABI) will use `vmov.s8` instead of
`vmov.u8` followed by `sxtb`.

Reviewers: SjoerdMeijer, dmgreen, ostannard

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70132