[all-commits] [llvm/llvm-project] f65493: [X86] Teach X86MCInstLower to swap operands of com...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f65493a83e3bdb402fb1dfa92bcc25707e961147
      https://github.com/llvm/llvm-project/commit/f65493a83e3bdb402fb1dfa92bcc25707e961147
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2019-11-04 (Mon, 04 Nov 2019)

  Changed paths:
    M llvm/lib/Target/X86/X86MCInstLower.cpp
    M llvm/test/CodeGen/X86/avx-intel-ocl.ll
    M llvm/test/CodeGen/X86/avx512-mask-op.ll
    M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
    M llvm/test/CodeGen/X86/avx512-vselect.ll
    M llvm/test/CodeGen/X86/madd.ll
    M llvm/test/CodeGen/X86/masked_compressstore.ll
    M llvm/test/CodeGen/X86/masked_expandload.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
    M llvm/test/CodeGen/X86/pr29112.ll
    M llvm/test/CodeGen/X86/sad.ll
    M llvm/test/CodeGen/X86/uadd_sat_vec.ll
    M llvm/test/CodeGen/X86/vec_umulo.ll
    M llvm/test/CodeGen/X86/vector-fshl-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-512.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-512.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
    M llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
    M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
    M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
    M llvm/test/CodeGen/X86/vector-rotate-256.ll
    M llvm/test/CodeGen/X86/vector-rotate-512.ll
    M llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll
    M llvm/test/CodeGen/X86/vector-trunc-math.ll
    M llvm/test/CodeGen/X86/vector-trunc-packus.ll
    M llvm/test/CodeGen/X86/x86-interleaved-access.ll

  Log Message:
  -----------
  [X86] Teach X86MCInstLower to swap operands of commutable instructions to enable 2-byte VEX encoding.

Summary:
The 2 source operands commutable instructions are encoded in the
VEX.VVVV field and the r/m field of the MODRM byte plus the VEX.B
field.

The VEX.B field is missing from the 2-byte VEX encoding. If the
VEX.VVVV source is 0-7 and the other register is 8-15 we can
swap them to avoid needing the VEX.B field. This works as long as
the VEX.W, VEX.mmmmm, and VEX.X fields are also not needed.

Fixes PR36706.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68550