[all-commits] [llvm/llvm-project] 39af8a: [DAGCombine][ARM] Enable extending masked loads

[Sam Parker via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 39af8a3a3b666929752e6bdff0bd65fedbbc34e8
      https://github.com/llvm/llvm-project/commit/39af8a3a3b666929752e6bdff0bd65fedbbc34e8
  Author: Sam Parker <sam.parker at arm.com>
  Date:   2019-10-17 (Thu, 17 Oct 2019)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-load.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-store.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll

  Log Message:
  -----------
  [DAGCombine][ARM] Enable extending masked loads

Add generic DAG combine for extending masked loads.

Allow us to generate sext/zext masked loads which can access v4i8,
v8i8 and v4i16 memory to produce v4i32, v8i16 and v4i32 respectively.

Differential Revision: https://reviews.llvm.org/D68337

llvm-svn: 375085